Patents Examined by Ishwar B. Patel
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Patent number: 7425684Abstract: In Electronics, there exists three distinctive areas namely, discrete components or devices, circuits, and systems. A circuit is built from devices and a system is built from circuits. This invention aims at reducing the implementation of electronic systems down to just three steps namely, systems design, printed-circuit-board planar assembly, and systems test when-as a plurality of Universal Systems Printed-Circuit Blocks of pre-defined sizes is used. Each of said Universal Systems Printed-Circuit Blocks being usable and reusable for prototypes and production is built from a printed circuit board having thereon a functional circuit and a variety of circuit patterns and interconnection structures such that, any of said blocks, when joined together with other blocks on the same plane by standard connectors or electrically conductive compounds to form a systems board, can send and receive signals and voltages to and from any other blocks.Type: GrantFiled: January 30, 2008Date of Patent: September 16, 2008Inventor: Sang Henry Ta
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Patent number: 7405365Abstract: A wiring substrate of the present invention includes a short ring (SR) formed along a periphery of the substrate, an independent line pattern (e.g., a gate terminal) that is coplanar with and independent of SR, a continuous line pattern (e.g., a storage capacitor stem) that is located closest to the independent line pattern and is coplanar and continuous with SR, and an insulating film covering the independent line pattern and the continuous line pattern. The insulating film includes a first through hole reaching the independent line pattern and a second through hole reaching the continuous line pattern.Type: GrantFiled: September 17, 2003Date of Patent: July 29, 2008Assignee: Sharp Kabushiki KaishaInventors: Hajime Imai, Osamu Sugimoto, Katsuhiro Okada, Isao Ogasawara
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Patent number: 6555759Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.Type: GrantFiled: February 21, 2001Date of Patent: April 29, 2003Inventors: George Tzanavaras, Mihalis Michael
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Patent number: 6512185Abstract: The invention provides a printed-wiring board that is capable of preventing the lift-off phenomenon without changing the related process for fabricating related printed-wiring boards. A printed-wiring board of the present invention has the structure in which land portions are formed on both sides (front side and back side) of a board, a through hole is formed through the board, and an electrically conducting layer is formed on the inside peripheral surface of the through hole by means of plating to connect between the above-mentioned land portions of a wiring pattern, wherein the entire surface of the land part including the opening circumference of the through hole is covered with an insulating layer that covers the other part of the wiring pattern on the component side and on the other hand the land part is not covered with an insulating layer and remains exposed on the soldering side.Type: GrantFiled: March 14, 2001Date of Patent: January 28, 2003Assignee: Sony CorporationInventor: Kazuhiro Itou
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Patent number: 6480396Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.Type: GrantFiled: March 12, 2001Date of Patent: November 12, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Ninomiya
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Patent number: 6479757Abstract: An apparatus includes a connection sheet having a separator layer and an adhesive film layer formed on the separator layer such that said adhesive film layer can be peeled from the separator layer. The cohesive strength of the adhesive film layer decreases when the adhesive film layer is heated to a predetermined temperature. Electronic parts each have an electrode surface and at least one electrode on the electrode surface.Type: GrantFiled: October 12, 2000Date of Patent: November 12, 2002Assignee: Hitachi Chemical Company, Ltd.Inventors: Isao Tsukagoshi, Kouji Kobayashi, Kazuya Matsuda, Naoki Fukushima, Jyunichi Koide
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Patent number: 6420658Abstract: A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.Type: GrantFiled: November 30, 1999Date of Patent: July 16, 2002Assignee: Oki Electric Industry Co., Ltd.Inventor: Norio Takahashi
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Patent number: 6388201Abstract: To provide a wired circuit board capable of surely preventing occurrence of a short circuit between a metal terminal layer and a metal supporting layer with a simple construction, to provide improvement in connection reliability and in voltage proof property, a wired circuit board comprises a base layer formed on a supporting board, a conductive layer formed on the base layer, a surface of the conductive layer being exposed by opening the supporting board and the base layer, and a metal plated layer formed on the conductive layer exposed in the openings of the supporting board and the base layer, wherein a specified space is defined between a periphery of the metal plated layer and a periphery of the opening of the supporting board.Type: GrantFiled: May 30, 2001Date of Patent: May 14, 2002Assignee: Nitto Denko CorporationInventors: Takeshi Yamato, Kenichiro Ito
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Patent number: 6339197Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 &mgr;m thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.Type: GrantFiled: May 26, 2000Date of Patent: January 15, 2002Assignee: Hoya CorporationInventors: Takashi Fushie, Takeshi Kagatsume, Shigekazu Matsui
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Patent number: 6320137Abstract: A printed circuit including a dielectric substrate and a conductive trace attached to a surface of the dielectric substrate. The trace includes a base layer and a coverplate layer on a portion of the base layer. The coverplate layer defines a coverplate edge on the base layer. A protective layer is formed on a portion of the coverplate layer. The protective layer extends beyond the coverplate edge onto at least a portion of the base layer of the trace. A key aspect of the present invention is that the protective layer overlaps the coverplate edge of each trace to reduce the potential for corrosion of the base layer at the coverplate edge.Type: GrantFiled: April 11, 2000Date of Patent: November 20, 2001Assignee: 3M Innovative Properties CompanyInventors: Lora C. Bonser, Terry F. Hayden, Robert J. Schubert
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Patent number: 6303881Abstract: An insulator substrate or printed circuit board (PCB) having a filled and plated via is provided. The plated via is filled with an electrically conductive fill composition. A conductive cap layer is formed on both ends of the conductive fill composition in the via and the major surfaces of the insulator substrate and can be bonded to a surface mount contact as a land or a pad.Type: GrantFiled: August 25, 2000Date of Patent: October 16, 2001Assignee: Viasystems, Inc.Inventors: John LeRoy Parker, Jr., Pamela L. Miscikowski
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Patent number: 6288345Abstract: A compact thick film substrate for filtering, shielding, and routing multiple lines of dc and control signals between isolated ports of a microwave integrated circuit. The substrate circuit includes a dielectric substrate having upper and lower substrate surfaces and first and second side surfaces. A first ground plane layer is formed on the upper substrate surface.Type: GrantFiled: March 22, 2000Date of Patent: September 11, 2001Assignee: Raytheon CompanyInventors: Tamrat Akale, Robert C. Allison, Lawrence Dalconzo, James M. Harris
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Patent number: 6274819Abstract: An article and method for making and repairing connections between first and second circuits, such as flex circuits. The article 10 includes: a flexible dielectric substrate 12 having first and second edges 14/16, and a plurality of conductive circuit traces 18 arranged on or within the substrate, wherein each of the traces extends from proximate the first edge 14 to proximate the second edge 16. Each of the circuit traces 18 includes: a first connection feature 20 disposed proximate the first edge 14; a second connection feature 22 disposed proximate the second edge 16; and at least one third connection feature 24 disposed between the first and second edges 14/16. Each of the first, second, and third connection features 20/22/24 is a plated through hole, a plated blind via, or a mounting pad. This article 10 may be used to connect together the first and second circuits 50/60 using the first and second connection features 20/22, such as by soldering.Type: GrantFiled: September 1, 1999Date of Patent: August 14, 2001Assignee: Visteon Global Technologies, Inc.Inventors: Delin Li, Jay DeAvis Baker, Achyuta Achari, Brenda Joyce Nation, John Trublowski
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Patent number: 6271483Abstract: A wiring board has vias which penetrate the wiring board from one side to the other side. The vias are radially arranged in the direction from one side to the other side so that the interval between the vias on one side can be made smaller than the interval between the vias on the other side. In order to prevent the vias from being electrically short-circuited to each other, even if the interval between the vias provided on one side of the wiring board is extremely reduced, a plurality of vias are radially arranged in the direction from one side of the wiring board to the other side so that an interval between the vias on one side of the wiring board can be made smaller than interval of the vias on the other side. A conductor forming the core portion of the via is coated with a sheath portion made of insulating material.Type: GrantFiled: December 15, 1998Date of Patent: August 7, 2001Assignee: Shinko Electric Industries Co., LTDInventors: Michio Horiuchi, Toshiaki Suyama, Masakuni Tokita
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Patent number: 6225571Abstract: The present invention provides a heatsink for use with a heat-generating electrical component. The heatsink comprises a spine having opposing sides, cooling fins extending from the spine, and a dielectric layer adhered to at least one of the opposing sides. The dielectric layer has a thermal conductivity of at least about 1 W/m° C. The heatsink may further comprise a metal layer adhered to the dielectric layer. The metal layer provides a surface to which an electric component can be adhered. The heatsink can further include a heat-generating component adhered to the metal layer. In another aspect, the heat-generating component is a surface-mount electrical component adhered to the metal layer with solder.Type: GrantFiled: February 19, 1999Date of Patent: May 1, 2001Assignee: Lucent Technologies Inc.Inventors: Jeffrey L. Bream, Stephen A. Ferranti, Madhu Ganesa-Pillai, Leon Klafter, Alan M. Lyons, John Paul Mello, Steven J. Vargo
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Patent number: 6207905Abstract: In the glass-ceramic composition, a weight ratio of a glass and a ceramic is 40 to 60:60 to 40. The glass is composed of 40 to 60 wt % of SiO2, 5 to 9 wt % of Al2O3, 1 to 10 wt % of B2O3, 3 to 5 wt % of Na2O+K2O, 3 to 15 wt % of CaO+MgO+ZnO, and 15 to 40 wt % of PbO, and does not contain Li2O. A softening point of the glass is 650 to 780° C. The circuit substrate includes a laminate substrate formed by laminating insulating substrates, and a conductor circuit formed on a surface of each insulating substrate. The insulating substrate is formed of the glass-ceramic composition. A wiring layer and a via hole conductor are provided inside the laminate substrate.Type: GrantFiled: August 2, 1999Date of Patent: March 27, 2001Assignee: NGK Spark Plug Co., Ltd.Inventors: Shigeru Taga, Hiroyuki Takahashi, Yoshitaka Yoshida