Patents Examined by Ishwar Patel
  • Patent number: 7405944
    Abstract: A retaining device holds a printed circuit board to a structure that has channels for receiving the retaining device. The retaining device includes a body having portions configured for receipt into the channels of the structure, flexible portions and protuberances protruding away from a first surface adjacent each flexible portion. A method for holding the PCB to the heat sink is disclosed. A lighting assembly that includes the retaining device is also disclosed.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: July 29, 2008
    Assignee: Lumination LLC
    Inventors: Mark J. Mayer, Alan B. Toot
  • Patent number: 7375287
    Abstract: An arrangement to receive and accommodate the power and control electronics of an electric motor comprises a first circuit board mounted with control electronic components, a second circuit board mounted with power electronic components which has a substrate that not only has electrically insulating properties but also good thermal conductivity, a cooling element in thermally conductive contact with the substrate of the second circuit board and a motor housing connected to the cooling element. Since the first circuit board can be constructed in a conventional manner and satisfactory cooling of the power electronic components arranged on the second circuit board has been provided for by the provision of the second circuit board that conducts heat to the cooling element, a compact, cost-saving overall design and construction has been achieved which is reliable when the electric motor is in operation.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: May 20, 2008
    Assignee: Minebea Co., Ltd.
    Inventor: Robert Rathmann
  • Patent number: 7371968
    Abstract: A detachable superconducting lead includes a vacuum-sealed thermal transition through which a stabilized conductor passes. Two identical leads are attached and surrounded by a sealed Dewar and allowed to cool either naturally or by way of a cooling element. Detaching the leads requires the joint to be heated up by a heat transfer unit or by a heat gun after the Dewar is removed. Once warmed, the lead can be disassembled with tooling appropriate to the joint. In many instances, regular fasteners can be used. Removable Dewars may be constructed with insulation (including vacuum) using O-rings and flanges.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: May 13, 2008
    Inventor: Michael J. Hennessy
  • Patent number: 7363706
    Abstract: This invention provides a multilayer printed wiring board having flat via holes. This is a multilayer printed wiring board formed by alternately laminating multiple metal foils and insulating layers, in which an interlayer connection via pad provided in a first insulating layer, a wiring circuit and an interlayer connection via bottom pad of a second insulating layer are provided in the same surface layer and at least the interlayer connection via pad and the interlayer connection via bottom pad of the second insulating layer have the same thickness.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: April 29, 2008
    Assignee: CMK Corporation
    Inventor: Eiji Hirata
  • Patent number: 7351313
    Abstract: The object of the present invention is to provide a nano-scale molecular assembly such as a conductive nano-wire. Specifically, there is provided an electrolytic apparatus for forming a molecular assembly, including two electrodes and an electrolytic cell holding an electrolyte and the two electrodes, wherein the gap between the two electrodes is from 1 nm to 100 ?m, by allowing the electrolytic cell to hold an electrolyte containing molecules that is to constitute the molecular assembly, and applying a voltage across the two electrodes in the state wherein the electrolyte and the two electrodes are in contact.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: April 1, 2008
    Assignee: National Institute of Information and Communications Technology, Incorporated Administrative Agency
    Inventors: Hiroyuki Hasegawa, Tohru Kubota, Shinro Mashiko
  • Patent number: 7205485
    Abstract: A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: April 17, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chin-Tien Chiu, Chin-Huang Chang, Chih-Ming Huang
  • Patent number: 7183497
    Abstract: A multilayer wiring board (11) is provided which includes a core substrate (12) including a plurality of through-holes (15). The through-holes (15) include through-hole conductors (17) on the inner walls of corresponding penetration holes (16) of a diameter of 200 ?m or less. Interlayer insulating layers (31, 32) are disposed on opposite sides of the principal planes (13, 14) of the core substrate (12). Wiring layers (23, 24) are disposed on the surface of interlayer insulating layers (31, 32). The through-holes (15) are filled with a hardened filling material (18). Lid conductors (21, 22) close the openings of the through-holes (15). The value of linear expansion of the hardened filling material (18) is 1.2% or less in the temperature region from room temperature to the solder reflow temperature. The board has excellent connection reliability and exhibits little or no cracking or delamination in the lid conductor closing the openings of the through-holes and in the surrounding conductor area.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 27, 2007
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Toshifumi Kojima, Makoto Wakazono
  • Patent number: 7151225
    Abstract: Provided is a superconducting cable having a structure such that cable cores, each having a superconducting layer, are housed in a thermal insulation pipe and the superconducting layer of each cable core has portions having different critical current values. When an excessive current flows in the superconducting layer in case of a short-circuit failure, the current exceeds the critical current value of the portion having a smaller critical current value first, which results in damage to the portion, suppressing the occurrence of damage to the other normal portion. A superconducting cable line using this superconducting cable and a splitter for accommodating the cable cores therein is also provided.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: December 19, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Jun Fujikami
  • Patent number: 7129419
    Abstract: The present invention relates to a printed circuit board with low noise. A voltage source layer and a ground layer of the printed circuit board are divided into an analog area and a digital area respectively via an isolation line, and adapted to conduct voltage source signal and ground signal respectively. Because the isolation line is an open pattern and a capacitor adapts to position near the opening, the noise and the electro-magnetic parameter of the printed circuit board are reduced.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: October 31, 2006
    Assignee: Tatung Co., Ltd.
    Inventors: Shih-Chieh Chao, Chih-Wen Huang, Chuh-Lin Liao
  • Patent number: 7129420
    Abstract: A semiconductor device includes a semiconductor chip and a substrate having an interconnecting pattern formed thereover. The substrate has the semiconductor chip mounted on one surface thereof. The substrate has an outline larger than the semiconductor chip. First terminals are formed in a region outside the region of the substrate in which the semiconductor chip is mounted. Second terminals are a part of the interconnecting pattern which exposes its surface opposite to its surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals. The semiconductor chip is electrically connected to the first and second terminals.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: October 31, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7126061
    Abstract: A printed circuit board for avoiding producing burrs, the printed circuit board includes a packaging substrate, at least one plated through hole, at least one first conductive portion, at least one non-conductive portion, at least one second conductive portion and at least one cut section. The plated through hole is formed on the packaging substrate. The first conductive portion and the second conductive portion respectively are adjacent to two sides of a peripheral of the plated through hole and separated by the non-conductive portion. Furthermore, the cut section is arranged on the non-conductive portion, thus the packaging substrate is cut without passing through the first conductive portion, and it will not cause the burrs on the first conductive portion.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: October 24, 2006
    Assignee: Lite-On Technology Corporation
    Inventor: Yung-Jen Lin
  • Patent number: 7126213
    Abstract: A rectification chip terminal structure for soldering a rectification chip on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent bending and deformation under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: October 24, 2006
    Assignee: Sung Jung Minute Industry, Co., LTD
    Inventor: Wen-Huo Huang
  • Patent number: 7115818
    Abstract: Metal foil is laminated via an insulating layer so as to cover the first layer circuit wiring formed on a conductive substrate, and a resist layer is formed so as to cover the second layer circuit wiring formed by pattern-etching the metal foil. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, in interlayer via holes each formed by applying a laser beam to the resist layer, thereby to establish interlayer connection between the first layer circuit wiring and the second layer circuit wiring. Subsequently, the resist layer is removed, and then, using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, in hole portions of an insulating layer formed so as to cover the second layer circuit wiring, thereby to form external connection terminals.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: October 3, 2006
    Assignees: Sony Corporation, Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Hidetoshi Kusano, Shinji Kumon
  • Patent number: 7038143
    Abstract: A wiring board includes a first conductor formation substrate having a first substrate and a first electrode; a second conductor formation substrate having a second substrate and a second electrode; and a dielectric sandwiched between the first conductor formation substrate and the second conductor formation substrate. The dielectric includes a dielectric film that is not melted during thermo-compression bonding, and an adherent insulator melted during thermo-compression bonding. The surface of the dielectric film is subjected to a treatment to improve wettability. Adherence of the adherent insulator in thermo-compression bonding to the dielectric film is facilitated. The distance between the first electrode and the second electrode is made uniform by interposing the dielectric film between the first and second electrodes. A wiring board ensured as to lifetime and improved in reliability, and a simple method of fabricating such a wiring board are achieved.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: May 2, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Utsumi, Hirofumi Fujioka, Seiji Oka, Hideki Tsuruse, Taichi Kase, Takeshi Muraki
  • Patent number: 6995320
    Abstract: A wiring board includes an insulating board defined by a first surface and a second surface opposing to the first surface; first signal strips disposed on the first surface; a first power distribution plane provided on the first surface so as to occupy a residual area of the first signal strips; lands disposed on the second surface; via metals penetrating the insulating board so as to connect the lands to the corresponding first signal strips; a second power distribution plane provided on the second surface.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kusakabe, Isao Ozawa
  • Patent number: 6903278
    Abstract: In substrate packaging and mounting, such as for a flip chip mounted on a thin-core or coreless substrate, a high degree of rigidness and support is imparted to the substrate, to overcome bending/flexing/distortion during mounting/packaging of the chip and to prevent possible chip damage, by a stiffener. Such a stiffener may be of one or multiple pieces in any suitable shape/form to allow its non-interfering positioning on the substrate, and made by any suitable process of any suitable material, including conductive material and material capable of withstanding the temperatures of chip mounting/bonding operations. Such a stiffener prevents bending/flexing/distortion of thin-core and coreless substrate arrangements during mounting/interconnection processes to achieve thinner and more light-weight electronics specifically afforded by thin-core/coreless substrate arrangements while lowering manufacturing time/costs.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventor: Ajit V. Sathe
  • Patent number: 6852931
    Abstract: A configuration and also a method for the configuration in which, the configuration has at least one electronic device with associated contact connections and at least one printed circuit board with external contacts. The printed circuit board is electrically coupled to the electronic device. At least the metallic surfaces of the configuration are covered by a plasma-polymerized polymer layer.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Jörg Zapf
  • Patent number: 6399889
    Abstract: A head interconnect circuit for connecting transducer elements of a data head to drive circuitry including an alignment finger on a lead tip for aligning leads relative to connectors or solder pads for electrically connecting heads to drive circuitry. A method for connecting a head interconnect circuit to a printed circuit supported on an head actuator including aligning an alignment finger on the lead tip with a printed surface of a drive circuit for soldering leads on the lead tip to solder pads or connectors on the drive circuit.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: June 4, 2002
    Assignee: Seagate Technology LLC
    Inventors: Kurt J. Korkowski, Kenneth R. Fastner, Adam K. Himes, Gregory P. Myers, Andrew R. Motzko