Abstract: A computer processor which has a apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.

Abstract: A pipelined processor for simultaneously performs one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations including at least an instruction fetch stage, an operand address stage, an operand fetch stage, an execution stage and a result handling stage. The processor also maintains a plurality of indicators which are selectively updated during the result handling stage for a given instruction to reflect the results obtained during the execution stage thereof. When the second instruction of first and second successively fetched instructions is a conditional transfer, a determination is made as to which indicators may be affected by the execution of the first instruction, and a determination is also made as to which indicator the conditional transfer is to test to decide whether there is a GO or a NOGO condition.

Abstract: When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.

Abstract: A valid mask generator comprising a series of mask generation blocks. Each block generates a predetermined number of valid mask bits given a predetermined number of start pointer bits and end bits, wherein said predetermined number of valid mask bits generated by each block is less than the total number of bits in the valid mask. The series of mask generation blocks may be connected in series, wherein each block outputs a carry-out signal, and wherein each block receives the carry-out signal from the node before it as a carry-in signal. A method for generating a valid mask from a start pointer and a plurality of end bits is also contemplated.

Abstract: A method of planarizing a semiconductor wafer having interconnect tracks of formed thereon, comprises applying a layer of inorganic spin-on glass to the wafer, curing the spin-on glass at a temperature not exceeding about 450.degree. C., then placing the wafer in a dielectric deposition chamber, subjecting the wafer to in situ disconnection and outgassing of water and reaction by-products, and then capping the wafer in a moisture-free environment with a protective dielectric layer resistant to moisture diffusion.