Patents Examined by J. Harold Louis-Jacques
  • Patent number: 5331571
    Abstract: An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I/O in normal mode and the test bus I/O in the test mode. The test bus is also connected through multiplexers to input nodes of function blocks. In test mode, the function block nodes are accessed through the test bus. For emulation of an embedded microcontroller or microprocessor, the internal connections of the microcontroller (or microprocessor) are brought out to those external pins which in normal operation are connected only to the microcontroller and not to any other function block. An in-circuit emulator (ICE) emulating the microcontroller is connected to the other function blocks through those external pins.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: July 19, 1994
    Assignee: NEC Electronics, Inc.
    Inventors: Alan P. Aronoff, Marc S. Birnkrant, Osamu Matsushima, Kyosuke Sugishita, Hisaharu Oba, Katta N. Reddy, Richard I. Olsen, Brent N. Dichter
  • Patent number: 5329450
    Abstract: When mobile robots having no task exist in the system and tasks not completed are remaining, a control station instructs the mobile robots to evaluate the remaining tasks. The mobile robots having no task then evaluate the remaining tasks and report corresponding evaluation values to the control station. The control station sequentially selects the combination of one of the mobile robots, having no task and one of the remaining tasks which are not assigned to the mobile robots so that the combination presenting the best evaluation value is selected, and assigns the task of the selected combination to the mobile robot of the selected combination.
    Type: Grant
    Filed: May 7, 1992
    Date of Patent: July 12, 1994
    Assignee: Shinko Electric Co., Ltd.
    Inventor: Masanori Onishi
  • Patent number: 5313407
    Abstract: A machine analyzer is connected to an active vibration cancellation system in order to identify the operating status of the moving machinery while using a minimum of additional parts and taking advantage of signal processing already occurring in the active vibration cancellation system. A preferred embodiment employs a neural network pattern classifier in connection with detecting operating states such as cylinder misfires in an internal combustion engine.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: May 17, 1994
    Assignee: Ford Motor Company
    Inventors: Timothy A. Tiernan, Earl R. Geddes, Mark L. Mollon