Abstract: A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start of the simulation, outputs of each flip-flop in the scan chain are initialized to a same known symbol (e.g., ‘X’). The flip-flops in the scan chain are clocked to shift binary digital symbols (zeros and ones) into the first flip-flop and through the successive flip-flops in the scan chain. During the shifting and clocking process, successive, contiguous pairs of flip-flop outputs are compared, one pair after each clock cycle. A double shift error is declared between the first flip-flop in the pair and the second flip-flop in the pair if the output symbols of the pair are the same.
Abstract: Disclosed are techniques for representing and modeling one or more systems in which each system corresponds to an application mode. This may be done for one or more geometries using local and/or non-local couplings. For each application mode, physical quantities are modeled and may be defined using a graphical user interface. Physical properties may be used to model the physical quantities of each system. The physical properties may be defined in terms of numerical values or constants, and mathematical expressions that may include numerical values, space coordinates, time coordinates, and actual physical quantities. Physical quantities and any associated variables may apply to some or all of a geometric domain, and may also be disabled in other parts of a geometrical domain. Partial differential equations describe the physical quantities. One or more application modes may be combined using an automated technique into a combined system of partial differential equations as a multiphysics model.
Type:
Grant
Filed:
November 27, 2001
Date of Patent:
April 14, 2009
Assignee:
Comsol AB
Inventors:
Lars Langemyr, Daniel Bertilsson, Arne Nordmark, Per-Olof Persson, Jerome Long