Abstract: Provided is a method including the following steps: forming an insulating film having a thickness of 0.5 ?m or greater on an epitaxial layer provided with a well region, a source region, and a contact region, each being an impurity diffusion region; forming, in the insulating film, an opening that has a dimension of 2 mm×2 mm or greater in a plan view to expose at least part of the impurity diffusion region from the insulating film. The step of forming the opening in the insulating film is performed by the following separate steps: removing the insulating film so as to leave one-half or less of the thickness of the insulating film unremoved, through dry etching by the use of a photoresist; and removing the insulating film until the opening reaches the upper surface of the epitaxial layer, through wet etching by the use of the same photoresist.

Abstract: An apparatus for positioning micro-devices on a destination substrate includes a first support to hold a destination substrate, a second support to provide or hold a transfer body having a surface to receive an adhesive layer, a light source to generate a light beam, a mirror configured to adjustably position the light beam on the adhesive layer on the transfer body, and a controller. The controller is configured to cause the light source to generate the light beam and adjust the mirror to position the light beam on the adhesive layer so as to selectively expose one or more portions of the adhesive layer to create one or more neutralized portions. The transfer body and the destination substrate are moved away from each other and one or more micro-devices corresponding to the one or more neutralized portions of the adhesive layer remain on the destination substrate.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, a plurality of first projecting portions which include portions of the semiconductor substrate provided in a first region of the semiconductor substrate to extend in a first direction along the main surface of the semiconductor substrate and to be spaced apart from each other in a second direction, orthogonal to the first direction, along the main surface of the semiconductor substrate, a first isolation region provided between the first projecting portions adjacent to each other, and first and second transistors provided in and over an upper part of each of the first projecting portions which is exposed from an upper surface of the first isolation region to be adjacent to each other in the first direction.

Abstract: The present invention provides an organic light-emitting display substrate, a method of fabricating the same, an organic light-emitting display panel, and an organic light-emitting display device. The organic light-emitting display substrate comprises a pixel defining layer provided on a base substrate and configured to define a sub-pixel region, the pixel defining layer comprises an accommodation area corresponding to a sub-pixel, and a groove located on an outer peripheral side of the accommodation area. In a process of forming an organic light-emitting layer by means of inkjet printing, excessive ink flows into the groove on the outer peripheral side of the accommodation area, which facilitates matching between a volume of ink for forming the organic light-emitting layer and a thickness of an actual organic light-emitting layer.

Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Abstract: A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Abstract: A mounting device includes a thermocompression bonding head, a pressure reduction mechanism, and a resin sheet feed mechanism. The thermocompression bonding head is configured to heat a semiconductor chip while holding the semiconductor chip and to bond the semiconductor chip to a joined piece by compression. The thermocompression bonding head has a suction hole in a face that holds the semiconductor chip. The pressure reduction mechanism communicates with the suction hole and is configured to reduce pressure inside the suction hole. The resin sheet feed mechanism is configured to supply a resin sheet between the thermocompression bonding head and the semiconductor chip. An electrode that protrudes from a top face of the semiconductor chip is bonded by thermocompression after being embedded in the resin sheet.

Abstract: A vacuum package includes a substrate, a pair of through electrodes that penetrates the substrate, each of the pair of the trough electrodes having first end portion, and a getter that is joined to the first end portions of the pair of the through electrodes, and is heated by electronic conduction via the pair of the through electrodes A portion of the getter between the through electrodes is spaced apart from the substrate.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate. In addition, when the small depressions are formed in the first joining region of the back surface of the heat releasing plate, the hardness of the first joining region of the back surface increases. Hence, the scratch is prevented from being created on the back surface of the heat releasing plate on which the depressions are formed to overlap each other in the first joining region of the back surface.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: A light emitting diode includes a substrate, a lower semiconductor layer disposed on the substrate, a light emitting unit comprising a first upper semiconductor layer disposed in one region of the lower semiconductor layer and an active layer interposed between the lower semiconductor layer and the first upper semiconductor layer, a second current spreading portion comprising a third upper semiconductor layer disposed in another region of the lower semiconductor layer and an active layer interposed between the lower semiconductor layer and the third upper semiconductor layer, a first electrode disposed on the light emitting cell and electrically connected to the first upper semiconductor layer, and a second electrode separated from the light emitting cell and electrically connected to the lower semiconductor layer.

Abstract: If a SiO2 film is formed on a semiconductor substrate using TEOS (tetraethylorthosilicate: Si(OC2H5)4), carbon (C) may be mixed in the SiO2 film in some cases. In a SiO2 film, carbon may function as fixed charges. For example, if carbon (C) is mixed in a SiO2 film as a gate insulating film of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate threshold voltage (Vth) may fluctuate. A semiconductor device using a gallium nitride semiconductor layer is provided. The semiconductor device includes: a silicon dioxide film that is provided at least partially in direct contact with the gallium nitride semiconductor layer and has impurity atoms, wherein the silicon dioxide film contains as the impurity atoms: carbon at concentration higher than 0 cm?3 and lower than 2E+18 cm?3; and gallium at concentration equal to or lower than 1E+17 cm?3.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A method of surface mounting micro-devices includes adhering a first plurality of micro-devices on a donor substrate to a transfer surface with an adhesive layer, removing the first plurality of micro-devices from donor substrate while the first plurality of micro-devices remain adhered to the transfer surface, positioning the transfer surface relative to a destination substrate so that a subset of the plurality of micro-devices on the transfer surface abut a plurality of receiving positions on the destination substrate, the subset including one or more micro-devices but less than all of micro-devices of the plurality of micro-devices, selectively neutralizing one or more of regions of the adhesive layer on the transfer surface corresponding to the subset of micro-device to light to detach the subset of micro-devices from the adhesive layer, and separating the transfer surface from the destination substrate such that the subset of micro-devices remain on the destination substrate.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

Abstract: When a nitride semiconductor layer into which impurity ions have been implanted is subjected to annealing after a protective film is provided on the nitride semiconductor layer, vacancy defects may be disadvantageously prevented from escaping outside through the surface of the nitride semiconductor layer and disappearing. A manufacturing method of a semiconductor device including a nitride semiconductor layer is provided. The manufacturing method includes implanting impurities into the nitride semiconductor layer, performing a first annealing on the nitride semiconductor layer at a first temperature within an atmosphere of a nitrogen atom containing gas without providing a protective film on the nitride semiconductor layer, forming the protective film on the nitride semiconductor layer after the first annealing, and after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.