Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions.

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Abstract: Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.

Abstract: A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perforin a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.

Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

Abstract: Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.

Abstract: A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprises the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit has a first value, (a) a specified floating-point operation function is performed, and (b) a condition code is set to a value determined by said specified function. If the test bit has a second value, (c) a check is made to determine if said specified function is valid and installed on the machine, (d) if said specified function is valid and installed on the machine, the condition code is set to one code value, and (e) if said specified function is either not valid or not installed on the machine, the condition code is set to a second code value.

Abstract: A processor including a physical register file, a rename table, mapping logic, size tracking logic, and merge logic. The rename table maps an architectural register with a larger index and a smaller index. The mapping logic detects a partial write instruction that specifies an architectural register that is already identified by an entry of the rename table mapped to a second physical register allocated for a larger write operation, and includes an index for the allocated register for the partial write instruction into the smaller index location of the entry. The size tracking logic provides a merge indication for the partial write instruction if the write size of the previous write instruction is larger. The merge logic merges the result of the partial write instruction with the second physical register during retirement of the partial write instruction.

Abstract: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint.

Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.

Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products for rules-based processing. In one aspect there is provided a method. The method may include, for example, evaluating rules to determine whether to enable or disable one or more actions in a ready set of actions. Moreover, the method may include scheduling the ready set of actions, each of which is scheduled for execution and executed, the execution of each of the ready set of actions using a separate, concurrent thread, the concurrency of the actions controlled using a control mechanism. Related systems, apparatus, methods, and/or articles are also described.

Abstract: A system and method of decreasing server loads and, more particularly, to decrease server load by automatically determining subgroups based on object interactions and computational expenditures. The system includes a plurality of servers; a subgroup optimization module configured to segment a plurality of objects into optimal subgroups; and a server transfer module configured to apportion one or more of the optimal subgroups between the plurality of servers based on a load of each of the plurality of servers. The method includes determining a relationship amongst a plurality of objects; segmenting the objects into optimized subgroups based on the relationships; and apportioning the optimized subgroups amongst a plurality of servers based on server load.

Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

Abstract: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.

Abstract: In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

Abstract: A first entry, when outputting an instruction stored in the first entry to a first arithmetic unit and when an execution cycle number of the instruction stored in the first entry is equal to or more than a threshold value, outputs a use inability signal of the first arithmetic unit to a second entry, a reservation station includes a controller configured to, when the use inability signal of the first arithmetic unit is output and then a use inability discontinuation condition is satisfied, perform control to discontinue execution of the first arithmetic unit, store a state of the first arithmetic unit in a storage element, and discontinue output of the use inability signal of the first arithmetic unit, and the second entry, when output of the use inability signal of the first arithmetic unit is discontinued, outputs an instruction stored in the second entry to the first arithmetic unit.

Abstract: An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.