Abstract: The present disclosure relates to a method of manufacturing a semiconductor light emitting device, the method comprising: providing a growth substrate on which a first semiconductor region, an active region and a second semiconductor region are sequentially formed; bonding a first light transmitting substrate to the second semiconductor region; removing the growth substrate from the first semiconductor region; attaching a second light transmitting substrate through an adhesive layer to the first semiconductor region from which the growth substrate is removed; laser ablating the first light transmitting substrate from the second semiconductor region; exposing part of the first semiconductor region, and forming a first flip chip electrode and a second flip chip electrode on the exposed first semiconductor region and the exposed second semiconductor region, respectively.

Abstract: An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.

Abstract: A display device and a manufacturing method of a display device are provided. The display device includes a substrate including a pixel defined thereon; a light emitting diode disposed in the pixel; an insulating layer covering the light emitting diode; a light collecting structure on at least a part of the insulating layer; and a reflective layer disposed at a side surface of the light collecting structure. The side surface of the light collecting structure may have a reverse tapered shape.

Abstract: A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip. The redistribution layer structure comprises a first region including: a first bump connected to the semiconductor chip; a second bump; and a plurality of first redistribution layers connected between the first bump and the second bump. The RDL structure includes a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers. The RDL structure includes an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layer. The isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the first redistribution layer structure, and has at least a selected width.

Abstract: Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.

Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

Abstract: A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.

Abstract: A lead frame includes a die pad, a plurality of leads, at least one support lead, and a frame member. The frame member includes two first connection bars and two second connection bars. The plurality of leads include a plurality of specific leads. The plurality of specific leads are each connected to the first connection bar. At least one of the specific leads is connected to the second connection bar via the at least one support lead. The cross-sectional second-order moment of a cross section of the at least one support lead perpendicular to a Y direction around an X axis is equal to or more than the cross-sectional second-order moment of a cross section of the at least one support lead perpendicular to an X direction around a Y axis.

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

Abstract: A device is provided that includes: a substrate including dielectric material and a conductive via extending into the substrate from a surface of the substrate. The device further includes a conductive pad positioned at the surface of the substrate and offset in a plane of the surface from the conductive via, the conductive pad to receive a solder joint connection to an electronic component. The conductive pad includes a concave edge that defines a gap with a convex edge of the conductive via.

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system. The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

Abstract: A method includes disposing a first die on a first die-receiving surface in a first cavity at a first vertical height in a substrate and disposing a second die on a second die-receiving surface in a second cavity at a second vertical height in the substrate. The second cavity has an open top, and the second vertical height is greater than the first vertical height in the substrate.

Abstract: A Micro-Electro-Mechanical Systems (MEMS) device includes a substrate, an electronic circuit on the substrate, an electrode electrically connected to the electronic circuit, a movable element that is controlled by applying a voltage between the electrode and the movable element, an insulating layer between the electrode and the electronic circuit, and an etch stop layer. The insulating layer has a via electrically connecting the electrode and the electronic circuit, and the etch stop layer is made of at least one of Aluminum nitride or Aluminum oxide. The etch stop layer may cover the electrode and the electronic circuit, or the electrode may be mounted on the etch stop layer, electrically connected to the electronic circuit through the etch stop layer by the via.

Abstract: An integrated circuit device according to the inventive concept includes: a semiconductor substrate including a cell region and a connection region; a gate stack including a plurality of gate electrodes and a plurality of insulating layers extending on a main surface of the semiconductor substrate in a horizontal direction and alternately stacked thereon in a vertical direction, the gate stack having a stair structure in the connection region; and a plurality of contact plugs in the connection region, wherein, in a portion of the connection region, a first length, in the horizontal direction, of a first gate electrode that is located in the lowest layer among the plurality of gate electrodes is less than a second length, in the horizontal direction, of a second gate electrode that is located above the first gate electrode.

Abstract: A component comprising a structural element, a leadframe and a shaped body, in which component the structural element and the leadframe are enclosed at least in regions by the shaped body in lateral directions and the leadframe does not project beyond side faces of the shaped body. The leadframe has at least one first subregion and at least one second subregion which is laterally spaced apart from the first subregion, wherein the structural element is electrically conductively connected to the second subregion by a planar contact structure. Furthermore, the structural element is arranged, in plan view, on the first subregion and projects laterally beyond the first subregion at least in regions, so that the structural element and the first subregion form an anchoring structure at which the structural element and the first subregion are anchored to the shaped body. Further specified is a method for producing such a component.

Abstract: A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction, extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements adjacent to each other in the second direction and sharing a common active region between a first gate structure of the first element and a second gate structure of the second element in the second direction. Boundaries of the common active region include an oblique boundary extending in an oblique direction forming an angle between 0 and 90 degrees with the second direction.

Abstract: A display device with a novel structure is provided. The display device includes a first substrate provided with a plurality of pixels including a display element, and a second substrate including a first conductive layer provided with a plurality of first openings. The first conductive layer has a function of an antenna capable of transmitting and receiving a radio signal. The pixel and the first opening include a region where the pixel and the first opening overlap with each other. The second substrate includes an element layer. The element layer includes a transistor. The transistor has a function of an amplifier capable of amplifying the radio signal. The transistor each includes a semiconductor layer including a metal oxide in a channel formation region. The metal oxide contains In, Ga, and Zn.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: In a general aspect, a semiconductor device assembly includes a direct-bonded-metal (DBM) substrate having a ceramic layer, and a first metal layer having a uniform thickness that is disposed on a first surface of the DBM substrate. The assembly further includes a second metal layer disposed on a second surface of the DBM substrate opposite the first surface. The second metal layer includes a first portion having a first thickness, and a second portion having a second thickness, the second thickness being greater than the first thickness. The second portion of the second metal layer includes a metal alloy having a coefficient of thermal expansion (CTE) in a range of 7 to 11 parts-per-million per degrees Celsius (ppm/° C.). The assembly also includes a semiconductor die having a first surface coupled with the second portion of the second metal layer.