Abstract: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.

Abstract: Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

Abstract: Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.

Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Abstract: Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

Abstract: The invention concerns a method for processing a signal using an approximate MAP (maximum a posteriori) algorithm for determining a likelihood ratio ?kX of a set of states X of a lattice at a time k, with each of said states being associated at least one intermediate variable belonging to a group comprising a so-called forward variable and a so-called backward variable, propagated by said MAP algorithm and recursively calculated respectively in a direct orientation and in an indirect orientation at said time k relative to said lattice. The invention is characterized in that said process comprises a step which consists in reducing the number of selected states by said MAP algorithm so as to calculate said likelihood ratio, and, for at least some unselected states, in assigning to said forward variable and/or said backward variable at least one specific value, to calculate an approximate likelihood ratio.

Abstract: A de-interleaver has a TTI frame buffer storing a TTI frame before de-interleaving, a P bit information table storing P bit information containing the size and added position of P bits to be added to the TTI frame before de-interleaving, and a permutation rule table storing permutation rules of de-interleaving. The de-interleaver performs de-interleaving on the data stored in the TTI frame buffer based on the P bit information stored in the P bit information table and the permutation rules stored in the permutation rule table.

Abstract: An apparatus, method, and computer program product to identify types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract: A sliding window turbo decoder is provided which is capable of reducing large amounts of arithmetic calculations required for decoding and of achieving decoding processing that can reduce power consumption. An input code block is divided into a plurality of windows on which forward and backward processing is performed to realize a plurality of times of iterated decoding. At every time of iterated decoding, CRC (Cyclic Redundancy Check) is made by the CRC processing section and, according to the CRC processing result, a training size (length) for training processing on an initial value to be used in path metric calculations in a backward direction in a subsequent decoding is adjusted and controlled and, if the result is good, decoding is stopped. Power consumption is reduced while decoding capability is maintained.

Abstract: A plurality of defect management areas (14A, 14B, 14C) are arranged on a write once type recording medium (10). Spare areas (12, 13) are divided into a plurality of partial spare areas (12A to 13B) and the defect list (21) is divided into partial defect lists (21A to 21D) so as to correspond to this. When recording data is recorded in a partial spare area, only the partial defect list corresponding to the partial spare area is recorded in the defect management area. In one defect management area, all the defect lists constituting the latest defect list are recorded.

Abstract: A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.

Abstract: An increment/decrement circuit for use with a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. In one embodiment, the increment/decrement circuit includes a delay circuit block operable to receive and align the debug data. First and second mask circuits are connected in parallel to the delay circuit block in order to select and assert portions of the aligned debug data for incrementing and decrementing, respectively. An accumulation circuit is connected to the first mask circuit and the second mask circuit for generating an accumulated value based on the outputs of the mask circuits.

Abstract: A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

Abstract: In a tentative target value calculation section 28, a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search executing section 25, binary search is executed, and a searching region is limited to a certain region including this tentative target value ExpB. Next, in a sequential search executing section 29, the target value Exp is searched for in an increasing direction from the tentative target value ExpB which is a start point in the limited searching region. Accordingly, both drop prevention of measurement precision and reduction of searching time are achieved consistently, and a target value is securely and normally found in a case where a sequence constituting a searching object indicates an ascending-order sequence including a decrease in a part.

Abstract: Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.

Abstract: A system, apparatus and method for updating security configurations of a plurality of servers from a centralized directory server. The system includes a centralized directory server and a plurality of servers that provide resources and store files for use by users of the system. Each file/resource associated with the servers includes a security parameter list identifying authorized users of the file/resource. The security parameter lists are updated from the centralized directory server by first inputting changes to the system security configuration in the directory server and then downloading these changes to the plurality of servers. The changes are used by the plurality of servers to update the security parameter lists associated with the files/resources of the server.

Abstract: A method for communicating communication network availability information regarding an individual to at least one subscriber of the individual's availability information. According to one embodiment, the method includes detecting whether the individual is present on at least one communication network and determining availability of the individual for each access level of a profile of the individual. The method further includes publishing via a network the availability of the individual to the subscriber based on an access level of the subscriber and the presence information. In addition, the method includes filtering the availability of the individual when it is detected that the individual is no longer present on the communication network.

Abstract: A turret control system and method for a fire fighting vehicle is disclosed. The turret control system includes one or more control modules, such as an envelope control module, turret targeting module, a turret pan module, a turret deploy module, a turret store module. The preferred turret control system also provides improved turret control flexibility and improved operator feedback.