Abstract: This invention relates to a turbo decoding apparatus and method for a communication system. A high-rate memory buffer operating at the same frequency as a turbo decoder is arranged between a memory buffer of a receiver and the turbo decoder. The decoding apparatus reads data bits stored in the memory buffer of the receiver via the high-rate memory buffer, delays the read data bits for a time required in the turbo decoder, and then applies the delayed data bits to a Soft-In Soft-Out (SISO) decoder of the turbo decoder. The memory buffer of the receiver outputs data bits at an operating frequency or clock of the turbo decoder.

Abstract: A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.

Abstract: A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.

Abstract: A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Abstract: A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied during a test operation. The detection circuit also generates a flag upon detection that the sum of data errors exceeds a threshold number of acceptable data errors.

Abstract: An efficient encoding method is provided for error correction coding in high density magnetic recording/reproducing apparatus. A first encoding circuit applies a first error correction coding to the information code sequence and generates an error-correction code sequence. A concatenated encoder is used to divide the plural code sequence blocks having predetermined lengths. The concatenated encoder also executes a second error-correction coding for each code sequence block and generates a second redundant code sequence. A code switch is used to output the plural code sequence blocks and the second redundant code sequence alternatively in order to generate information code sequence that is comprised of the plural code sequence blocks.

Abstract: A semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction. A plurality of latch circuits latch output signals outputted from a plurality of DUTs having the same test signal “test” inputted thereto. A P-S conversion circuit sequentially outputs an expected value signal “exp”, which is an expected value of signals that the DUTs should output in response to the test signal “test”, and a plurality of latched signals, for a latch time period. An encoder circuit compares the latched signals with the expected value signal “exp”. A memory stores the latched signals and the expected value signal “exp” delivered from the P-S conversion circuit, when the latched signals do not agree with the expected value signal “exp”. A determination circuit determines the quality of each of the DUTs, based on the latched signals and the expected value signal “exp” stored in the memory.

Abstract: A method and apparatus for determining a bit error rate. The method comprises the steps of acquiring a data signal by an acquisition unit of a test instrument for a predetermined period of time, and storing the data signal in a memory of the test instrument. A clock signal is recovered from the stored data signal, and in accordance therewith, the stored data signal is sliced into a plurality of data segments of a predetermined length. Each of said data segments is synchronized to a frame or predetermined pattern to determine a bit error rate thereof.

Abstract: A computer apparatus includes a first integrated circuit (IC) and a second IC. The second IC includes a soft error rate (SER) immune component and a SER component to detect radiation that could result in soft errors at logic at the first IC.

Abstract: An interface circuit includes a selection circuit receiving first and second signals, generating a time division serial signal by selecting one of the first and second signals in response to the voltage level of a clock signal provided from the outside of a semiconductor device, and outputting the time division serial signal to a single input terminal of the semiconductor device via a single signal line, a first holding circuit, which is connected to the terminal for receiving the time division serial signal, for capturing and outputting the first signal of the time division serial signal in response to the rise of the clock signal, and a second holding circuit, which is connected to the terminal for receiving the time division serial signal, for capturing and outputting the second signal of the time division serial signal in response to the fall of the clock signal.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus.

Abstract: An analog base-band (ABB) chipset of a mobile communication system comprises a memory configured to store a test pattern, a test control unit configured to generate a control signal during a test mode, an ABB unit configured to perform a test operation by receiving the test pattern from the memory in response to the test control signal and to output data of the test pattern to the memory in response to the test control signal, and a path selection circuit configured to form a flow path of the test pattern in the ABB unit in response to the test control signal.

Abstract: An ergonomically designed transactional terminal according to the invention in one embodiment includes a housing having a top portion partially defined by a touch screen, a base, and an enlarged head portion extending forwardly from the base to define a lip. An insert style card reader having horizontally oriented feed slot opening toward the front of the housing is disposed in the lip of the housing. The feed slot may be angled downward slightly to reduce build up in the slot and to encourage a sweeping action by a card during card removal. The touch screen may be angled downward in coplanar relationship with the feed slot to improve visibility of the touch screen and to improve simultaneous observation of touch screen and card indicia.

Abstract: An audio encoder converts an input sound signal into a plurality of compressed frame data pieces in an sound signal compression coder, determines the importance of each bit in a classification unit of a transmission line coder based on the decoding quality in the presence of a transmission error, and classifies the bits into a plurality of classes. The audio encoder selects one of the three types of processing including convolution coding and addition of CRC check codes, convolution coding only, and no coding, in descending order of importance in the presence of a transmission error for each class. Then, the audio encoder adds preamble information and a synchronization signal in a multiplexer to generate a bit stream. It becomes possible to suppress degradation of a decoded sound signal without additional redundant bits.

Abstract: To perform error detection and correction on a data sector, syndromes are calculated and used to determine error values and error locations. Logarithmic calculations in Galois field need to be performed to determine the error locations using the syndromes. Finite field vectors are represented as “complex” numbers of the form Az+B. An algorithm is performed using the field vectors represented as complex numbers to generate the error locations. The algorithm requires the use of logarithm calculations. The results of the logarithmic calculations are looked up in two (or more) log tables. The log tables store all the possible results of the logarithm calculations. The log tables store significantly less bits than prior art techniques, reducing the amount of storage space required by a factor of 171. Techniques for controlling accesses to the log tables in an efficient manner are also provided.

Abstract: A method and device for comparing two generic digital signals over a wide range of data rates and for counting the number of bit errors between digital signals under the conditions of noise and jamming. The bit error tester of the invention compares the digital signal sent with the digital signal received back from the unit under test and outputs the error signal. In the preferred arrangement of the invention, a field programmable gate array is used and a switch and LED display are used to introduce and monitor a time delay in the sent signal to ensure that the signals are in time alignment prior to comparison.

Abstract: A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.

Abstract: A test device includes: the first reference clock generation unit for generating the first reference clock; the first test rate generation unit for generating the first test rate clock based on the first reference clock; the first driver unit for supplying the first test pattern to an electronic device based on the first test rate clock; the second reference clock generation unit for generating the second reference clock; the first phase synchronization unit for synchronizing the phase of the second reference clock with the phase of the first test rate clock; the second test rate generation unit for generating the second test rate clock based on the second reference clock having the synchronized phase; and the second driver unit for supplying the second test pattern to the electronic device based on the second test rate clock.