Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

Abstract: A memory device and an electronic system, the memory device including a substrate; a ground selection line on the substrate, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; and second insulation layers and second word lines alternately stacked on the first word line, wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, and the second portion of the first word line has a second thickness less than the first thickness.

Abstract: A semiconductor device includes a stack structure including mold layers and horizontal conductive layers, which are alternately stacked. A channel structure vertically extending in the stack structure is provided. A pillar structure vertically extending in the stack structure is provided. A contact plug connected to a corresponding one of the horizontal conductive layers is disposed. The pillar structure includes a pillar extending through the horizontal conductive layers, and extensions protruding from a side surface of the pillar. Each extension is horizontally aligned with a corresponding one of the horizontal conductive layers.

Abstract: A semiconductor structure and a manufacturing method therefor are provided by embodiments of the present application. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. In the second buffer layer, by decreasing a doping concentration of the transition metal or not doping intentionally the transition metal, a tailing effect is avoided and current collapse is prevented. By doping periodically C in the buffer layer, C may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.

Abstract: An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.