Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Abstract: A system and method are provided for boundary scan testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus (SMBus) interface. The drive tester system performs a boundary scan test on the on more digital data storage drives via the standard two-wire interface. The boundary scan test may include a vector test.

Abstract: A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.

Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Abstract: A communication unit (2020) performs directly wireless communicates with a portable terminal (3000). A collection information acquisition unit (2040) acquires collection information. A division transmission unit (2060) generates multiple pieces of partial collection information by dividing the collection information, and transmits pieces of partial collection information being different from each other to multiple portable terminals (3000). A redundancy transmission unit (2080) transmits the same collection information to the multiple portable terminals (3000). An index value acquisition unit (2100) acquires any one or two of a reliability index value and a capacity index value of the portable terminal (3000). Based on any one or two of the reliability index value and the capacity index value of each portable terminal (3000), a transmission control unit (2120) selects the division transmission unit (2060) or the redundancy transmission unit (2080) to perform the transmission.

Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Abstract: A method begins by determining to rebuild one or more encoded data slices to a dispersed storage network (DSN) memory unit. The method continues by determining a rebuild rate of the DSN memory unit. The method continues by determining, based on the rebuild rate, a rebuild rate status of the DSN memory unit. The method continues by when the rebuild rate status is a high rebuild rate status, reducing the rebuild rate to the DSN memory unit. The method continues by rebuilding, when the rebuild rate is not zero, the one or more encoded data slices in the DSN memory unit.

Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.

Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

Abstract: An integrated circuit (IC) includes an encoder circuit. The encoder circuit includes an encoding input configured to receive an input message including one or more data symbols. Each data symbol has N bits and N is a positive integer. The encoder circuit includes an encoding unit configured to perform Reed-Solomon encoding to the one or more data symbols to generate one or more coding symbols. The Reed-Solomon encoding uses a Galois field having an order that is less than 2N. A coded message that includes the one or more data symbols and the one or more coding symbols is provided at an encoding output of the encoder circuit.

Abstract: Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node (10) to a group of destination nodes (21-23), including the steps of marking messages (1) transmitted from the source node (10); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node (10) to the group of destination nodes (21-23) and conclude the presence of an error in the delivery of data.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by identifying a data object to access within a DSN. The method continues by identifying a vault ID based on the data object. The method continues by obtaining an object ID based on the data object. The method continues by selecting at least one generation ID based on generation status. The method continues, for each generation ID, by generating at least one set of slice names using the vault ID, the generation ID, and the object ID. The method continues, for each set of slice names, by generating a set of slice access requests that includes the set of slice names and accessing the DSN utilizing the set of slice access requests.

Abstract: A method begins by a dispersed storage (DS) processing module identifying an encoded slice requiring rebuilding. The method continues by the DS processing module determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group determining by the DS processing module whether a valid encoded data slice of the fan-out data slice group is available. When a copy of the encoded data slice of the fan-out encoded data slice group is not available, the method continues by the DS processing module rebuilding the encoded data slice. A storage unit then stores the rebuilt encoded data slice and creates copies of the rebuilt encoded data slice to produce a rebuilt fan-out encoded data slice group.

Abstract: An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

Abstract: An embodiment method includes receiving, by a first user equipment (UE), a message, for a second UE, transmitted over a plurality of resource blocks (RBs) on behalf of a communications controller and determining a plurality of log-likelihood ratios (LLRs) in accordance with the received plurality of RBs. The method also includes transmitting, a subset of the determined LLRs to the second UE.