Abstract: Higher order digital transmission system including a multiplexer having N parallel inputs to which tributary input signal streams are applied, and a demultiplexer having N parallel outputs from which the tributary signal streams are taken. The signal processing operations, such as scrambling, justifying, line coding, error monitoring and word synchronization are effected before the multiplexer and after the demultiplexer, consequently not at the full line rate.

Abstract: A ring-shaped TDM digital communication system and method for enabling stations connected thereto to obtain access to a common message channel available for all of the stations. Access is unambiguously determined by an arbitration procedure which selects the station which obtains access to the message channel and excludes all other stations. Such message channel is also used for the arbitration procedure, which is based on recognizing the channel as being unoccupied if the value of the information in a time slot field thereon remains the same in successive cycles around the ring of a TDM frame comprising such field. The messages which are transmitted are structured so that error detection and correction, addressing, congestion indication, etc., can easily be included.

Abstract: The present invention relates to a multiple-user communication system wherein one carrier source is shared by a cascade of users of the system. More particularly, the present communication system uses a single carrier propagating along the system's transmissin medium onto which each user directly impresses the associated data or communication signal destined for another user preferably using either subcarrier angle modulation (phase or frequency) or TDM techniques for intensity or angle modulation. In the present system using subcarrier angle modulation, each user can either transmit or receive at a fixedly assigned or selectively assigned subcarrier channel, which is different from the subcarrier channel assigned to each of the other users. Where TDM techniques are used, the communication signal from a user can be directly impressed on the single carrier using intensity or phase modulation.

Abstract: A telephone signal transmission device capable of transmitting and receiving dial pulses in a network system which includes a telephone exchange is disclosed. Transitions of a connection signal are detected to allow a connection signal to be transmitted only when the transmission of a speech signal is needless. When the connection signal has a stable state (i.e. high or low) within a frame, only one bit is transmitted. The device effectively utilizes substantially all of the transmission bits for speech.

Abstract: A digital audio transmission system which is compatible with common carrier digital hierarchy systems converts two channels of analog data, such as precision stereo audio, into high resolution digital data words sampled at a high frequency. The data words are parity checked with the addition of one bit and divided into odd and even bit words for each channel. The bit words are time domain multiplexed into a common carrier frame with separate words for the parity bits and alternating channel data consisting of an odd and an even bit word. Each bit word is checked for all zeros and modified accordingly to assure that ones density and consecutive zero restraints are achieved. The resulting common carrier frames are transmitted over the appropriate common carrier cross-connects to a receiver which decodes the frames, recovering the bit and parity words. The bit words are recombined into data words and checked for parity.

Abstract: In a two-way radio transmission system, a fixed base station transmits and receives over at least one communication channel a plurality of messages for different types of receivers (TGAx) used in different services (DY). The base station transmits an organization data flow identifying the message type (TGAx) and services (DY). A plurality of different subscriber transmitter receiver sets receive each message type (TGAx) and transmits messages to the base station. The receiver sets decode the organizational data flow, and process only those messages and services which are associated with a given message and service type. In this way, different classes of communication services may be offered, using a common base station.

Abstract: For adaptive line equalization of a time-division multiplexed analog signal, an offset-compensated filter circuit comprises a timing circuit for generating channel-switching signals respectively synchronized with the time slots of the TDM signal. A switched-capacitor filter comprising an operational amplifier and a switched-capacitor circuit is responsive to the channel-switching signals for sequentially establishing transfer functions specific to the time slots of the TDM signal. A plurality of switched-capacitor DC decoupling circuits are connected to the output of the switched-capacitor filter. These DC decoupling circuits are respectively associated with the channel-switching signals for coupling a respective one of the filtered components to an input terminal of a summing amplifier.

Abstract: Local area networks having a high level of network integrity, error detection and correction, message security, expandability and flexibility are disclosed. The system is comprised of a loop controller which may communicate with a host through a standard interface such as an RS232 interface, and to which a plurality of nodes are coupled in a reconfigurable network. Each node has a plurality of modes controlled by the network controller to serve various functions depending upon requests from the controller and/or the needs or condition of the respective node from time to time. In particular, the first node is coupled to the controller through a pair of wires, with each successive node being coupled to the preceding node through a similar pair of wires. In one mode, the respective node monitors the incoming signal from the controller as repeated through any preceding nodes, and itself acts as a signal repeater for the next downstream node.

Abstract: A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.

Abstract: An integrated service network ("ISDN") is structured to connect subscriber lines through a packet switching system to incoming or outgoing packet switching calls without passing them through a circuit switching system. This effectively uses the speech path of the circuit switching section instead of using it for packet switching calls. At the same time, the invention minimizes the influence of the introduction of the ISDN upon the software of the circuit switching section. The ISDN digital switching network applies to circuit switching calls which are switched at a local switch and to packet switching calls which are to be switched at a toll switch.

Abstract: The present invention relates to a fast packet assignment technique, and a TDMA or FDMA multi-port switching arrangement for implementing such technique. In the present technique, the total traffic in a two-dimensional traffic matrix (T) from and to each of N remote service areas, regardless of destination or origination, is totaled to form separate input (R) and output (S) traffic vectors, respectively. Non-conflicting assignments are then made from these vectors for each packet or channel available during a predetermined time period while also providing the capability of substantially reducing multi-path or antenna sidelobe interference. An M.times.M switch (16) is designed to implement such technique which directs C input packets from M inputs (20.sub.1-M) into separate memory locations (Z.sub.ij). During the time period of the next C input packets, the M.times.M switch directs the presently stored packets to the proper ones of M outputs (27.sub.

Abstract: A technique is disclosed for improving the recovery of data signals transmitted on orthogonally polarized carrier signals by creating redundancy with respect to timing and carrier information. In the receiver, the carrier and timing recovery circuitry, which controls the recovery of the data signals from the incoming orthogonally polarized carrier signals, operate in response to a selected one of the carrier signals or at least one data signal recovered from this selected carrier signal. This selection is based on an examination of the data signals recovered from each of the orthogonally polarized carrier signals. Use of the described technique advantageously lessens the possibility of the carrier and timing recovery circuits losing synchronous operation during fading as it is less likely that a fade will simultaneously affect both orthogonally polarized carrier signals. As a result, data signal recovery is improved.

Abstract: Methods and apparatuses for efficiently allocating bandwidth to data, control and multiplexer overhead and for providing flexible data rates and control rates are provided. The apparatuses of the invention are used in a time division miltiplexer which multiplexes for transmission over and for receipt from at least one aggregate line in accord with at least one frame, data and control information from a plurality of channels and multiplexer overhead information.

Abstract: A local area network comprising a plurality of terminals interconnected by a communication bus is disclosed. Each terminal comprises a memory, a main processor, and a co-processor. To transmit information in a communication mode, the main processor loads data into a transmit buffer area of the memory, and the co-processor reads the data from the transmit buffer area and transmits a packet on the communication bus. Similarly, the co-processor receives data from the communication bus and stores it in a receive buffer area from which it is read by the main processor for use. In an alternative mode, called the direct transfer mode, the co-processors are reconfigured so that data for transmission is read from the actual locations in memory where it is stored (not the transmit buffer area), and received data is stored in storage areas where it is expected to be used (not the receive buffer area).

Abstract: A data detector is disclosed wherein a received signal is analyzed to determine its statistical characteristics. These characteristics are compared to a predetermined statistical distribution. If the signal is statistically close to the statistical characteristics of a known signal a detect signal is generated and the received signal is passed for further processing and reception.

Abstract: A signal selection system is disclosed wherein a plurality of received signals are analyzed to determine their statistical characteristics. These characteristics are compared to a predetermined statistical distribution. The signal that is statistically closest to the statistical characteristics of a known signal is selected for further processing and reception.

Abstract: The circuit comprises a serial to parallel converter for extracting the signalling bits from the various channels of the data streams and for providing a serial stream of signalling bits, and a read-write memory having a plurality of locations at least as large as the number of channels in the data streams, each location having at least the number of cells necessary to store a byte of signalling data and the signalling message header. The converter outputs the signalling bits from consecutive channels of the data streams into a one-byte shift register adapted to shift the bits laterally as well as receive and output a byte of data in parallel from and unto a bus connected to memory.