Abstract: New and novel structure(s) for cleaning surfaces have been disclosed. The device may include: a wiping surface, which may be disposable; a brush roll/larger debris gathering mechanism: a wiping surface, which may be disposable; a brush roll/larger debris gathering mechanism; a local debris storage and/or staging area, and a larger remote debris storage structure. Additionally, there are mechanisms and structures disclosed for powering the brush roll, activating the brush roll from an out of use position to an in use position, and moving the waste from one area to another. The invention at hand uniquely and inventively improves upon the known devices in this field.

Abstract: A power supply control device includes a first signal output unit that outputs a re-power signal and an off-ready signal, the re-power signal being a signal for turning off the power supply of an apparatus for a predetermined period of time and then turning on the power supply of the apparatus, the off-ready signal indicating that the power supply of the apparatus is ready to be turned off; a second signal output unit that outputs a power-off enable signal for turning off the power supply of the apparatus to a power supply unit when the re-power signal and the off-ready signal are supplied to the second signal output unit; and a holding unit that holds the power-off enable signal for the predetermined period of time.

Abstract: A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.

Abstract: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.