Abstract: A method and apparatus is described for enabling efficient, bilateral communications in a network connecting a plurality of target address modules and a plurality of source address generators. The source address generators are enabled to generate requests to target addresses within the target address modules. The function of the network is to forward the requests to the target address modules holding the respective target addresses and to return the replies generated by the target address module to the respective source address generators. The network interconnects the source generators to each target address module and vice versa. The interconnection network includes a plurality of interconnected nodes, each node having M inputs and N outputs (where M may or may not be equal to N) and a processor for carrying out a communication protocol. The protocol comprises each node first placing incoming target addresses from messages appearing on the node's inputs into a queue associated with each respective input.

Abstract: A centralized loom control method employing a host computer for controlling the operation of a plurality of looms. Data base including data accumulated by recording past actual weaving conditions in stored in a memory device connected to the host computer. The host computer determines standard set value for which the looms are to be set by processing the specifications of a fabric to be woven entered therein and data fetched from the memory device through predetermined calculation or interpolation. The host computer compares a standard operating speed among the standard set values with a target operating speed at which the loom is to be operated, and changes the standard set values according to the result of comparison to provide new standard set values suitable for operation at the target operating speed.

Abstract: A controller controls data transfers between a data processing system bus and peripheral devices. In the controller, data buffers are divided into page frames. Paging circuitry provides for allocation and deallocation of pages to and from the data buffer. Included in the page circuitry is a paging RAM. The paging RAM and other paging circuitry components allow contiguously addressed pages of data to be stored in noncontiguous locations in the data buffer. There may be more than one data buffer and these data buffers may be exclusively seized by microprocessors in the controller via seizing logic.

Abstract: A thread cutting machine is provided with a control system in which, according to one aspect, the rotation of the spindle is controlled in the synchronous manner following up the feed amount of the spindle head and the rotation instruction is computed in accordance with the feed deviation, In another aspect, the feed of the spindle head is controlled in the synchronous manner following up the rotation of the spindle and the feed instruction is computed in accordance with the rotation deviation. In a further aspect, the rotation instruction is operated in accordance with the feed speed and the feed acceleration. In still a further aspect, the feed instruction is computed in accordance with the rotation speed and the rotation acceleration. In the preferred embodiments disclosed herein, the synchronism between the rotation of the spindle and the feed of the spindle head can be remarkably improved with various control modes, thus achieving the high speed thread cutting working with high accuracy.

Abstract: A numerical control method is provided which is capable of forming a circular are on a cylindrical surface of a cylindrical workpiece with high accuracy by the use of a simplified program. At first, a circumferential distance interval between the start and end points of a circular arc to be machined is calculated on the basis of a moving command value for a rotation axis indicative of an angular interval in the circumferential direction of the workpiece (S3). Then, a circular are interpolation processing is executed on the thus calculated distance interval and a moving command value for a linear axis indicative of an interval between the start and end points in the axial direction of the workpiece, to thereby calculate distribution amounts for the rotation and linear axes, respectively (S4).

Abstract: A data processor comprises an array of integrated circuits (ICs), each of which comprises an array of data processing elements (PEs) connected to allow transfer of data. The PEs of the data processor may be organized into array-wide rows and columns with data transfer along each row or column. Rows and columns may be subdivided into sections, such division being either intra-chip (all PEs on one IC) or inter-chip (PEs from different ICs), and each section may be arranged for cyclical data transfer within the section. Shift registers with parallel outputs for intra-chip data transfer may be combined with a multiplexer for selecting between parallel data paths and a parallel data output of a local memory for each PE. Similarly, shift registers with serial outputs for inter-chip data tranfer may be combined with a multiplexer for selecting between serial data paths and serial outputs of the shift registers.

Abstract: Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a memory reference restart command latch allows an implementation that requires no additional logic for conditional writing of states pending exception checking. The exception handling hardware is minimized because instructions which cause exceptions are never re-executed, and exception handling microcode executes in-line with the normal microcode flow.

Abstract: An apparatus and method for eliminating integrator windup in control systems having a control input, a feedback signal and an actuator that can saturate in response to dynamic non linearities such as slew rate limits. The apparatus of the invention is comprised of circuitry that determines the rate of change of the output of the integrator and compares it to predetermined maximum allowable rates of change. If these maximum allowable rates of change have been exceeded, the comparator circuitry generates a compensation error signal which when combined with normal error signal integrated by the compensator tends to reduce the rate of change on the output of the integrator.

Abstract: An interactive graphical tool is provided for designing the user interface of a program-controlled instrument. The tool runs on a computer workstation and is used to model the application code of the instrument as a first network in which sessions of user interaction with the application code are represented by respective elements of the network. The actual user interaction sessions themselves are modelled by respective second networks; each second network includes information for defining the interface states of the modelled user interaction session. The full user interface can thereafter be simulated by progressing through the first model until a user interaction element is met and then entering the corresponding second network; the interface state information contained in the second network is used to drive a simulation of the instrument interfaace on the display of the computer workstation.

Abstract: A character code generating device includes a standard character code correspondence table for storing the character codes each corresponding to individual key-inputs from a key board, a searching device for the for said standard character code correspondence table to generate the character codes corresponding to the key-inputs, a supplementary character code correspondence table and a judging device. The supplementary character code correspondence table serves to store the character codes different from those in the standard character code correspondence table with respect to the specified key-inputs from the key board. The judging device determines whether the search of the supplementary character code correspondence table is required or not.

Abstract: A disk drive controller bus architecture for interfacing disk drives having widely varying data format requirements with small computer systems is comprised of a disk drive parameter storage section, a disk drive parameter compartor/interface section and a set of associated data buses, coupled between a disk drive controller processor and the disk drive. The disk drive parameter storage section contains a set of control registers and a (format option) random access memory which may be written to and read by the control processor and serves to store drive control codes that are selectively coupled over a first of the set of associated data buses for application to the disk drive parameter comparator/interface section. The disk drive parameter comparator/interface section contains multiplexer and format conversion circuitry for interfacing data between the disk, storage/buffer components of the bus architecture itself, and the control processor.

Abstract: A data processor is provided with status logic for monitoring the instruction processing activity therein, and for providing a pulse width encoded status output signal having either a first duration if the next instruction is to be executed in a normal sequence, or a second duration if an exception condition has occurred which will delay or prevent the execution of the next instruction. In the preferred form, the status logic can detect various types of exception conditions in the CPU and will assert the status signal for respective durations for each such type. In a data processor having an internal instruction pipeline, the status logic may also monitor changes in the flow of instructions, and provide a "refill" signal to indicate that the prefetched instructions in the pipeline have be discarded.

Abstract: When NC data inputted from an NC data supply unit (1) are data (G68) indicative of a coordinate transformation, a discriminating unit (2a) applies rotational axis vectors, the coordinates of centers of rotation and the angles of rotation, all of which are commanded following the data G68, to a transformation matrix generator (2b) and instructs the latter to generate transformation matrices. In response, the transformation matrix generator (2b) generates coordinate transformation matrices [M.sub.1 ], [M.sub.2 ] using the given data. When the NC data are path data, on the other hand, the discriminating unit inputs these data to a coordinate transformation unit (2c), which proceeds to subject the positional coordinates contained in the path data to a coordinate transformation using the transformation matrices [M.sub.1 ], [M.sub.2 ] and apply the results to an axis controller (3). The axis controller (3) performs machining by moving a tool along a path obtained by rotations through angles .theta., .phi.

Abstract: In a system including a processor and at least one connector for providing inputs to the processor, which one of a plurality of different types of peripherals is plugged into the connector is determined by sensing any change in the connection of a peripheral to said connector, upon initial start-up of the system and each time a change from not plugged in to plugged in is detected interrogating the peripheral to obtain its type and storing the type of peripheral which is plugged in.