Patents Examined by James Menefee
  • Patent number: RE45861
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: January 19, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Shuichi Tsukada, Yasuhiro Uchiyama
  • Patent number: RE45879
    Abstract: An end of a light guide plate used for a liquid crystal display and a lighting unit, which is positioned on one side in a first direction, is provided with a depressed portion, and another end of the light guide plate, which is positioned on the other side in the first direction, is provided with a projecting portion. Using the depressed portion and the projecting portion, the light guide plate is placed in a predetermined position of a frame body. The depressed portion and the projecting portion are formed at positions opposite each other in the first direction, and the projecting portion is equal to or smaller than the depressed portion in size.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 2, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Nobutaka Urano, Yoichi Momose
  • Patent number: RE45943
    Abstract: A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first reflectivity and a second reflectivity of the irradiated overlay offset measurement target. The calculation unit is operable to determine an overlay offset using the detected first and second reflectivity by determining a predetermined overlay offset amount which provides an actual offset of zero.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Chih Huang, Chih-Ming Ke, Tsai-Sheng Gau
  • Patent number: RE45944
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuang Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
  • Patent number: RE45955
    Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tien Ying Luo, Gauri V. Karve, Daniel K. Tekleab
  • Patent number: RE45957
    Abstract: A laser includes a regenerative ring resonator that includes a discharge chamber having electrodes and a gain medium between the electrodes for producing a laser beam; a partially-reflective optical coupler, and a beam modification optical system in the path of the laser beam. The beam modification optical system transversely expands a profile of the laser beam such that the near field laser beam profile uniformly fills each aperture within the laser and such that the regenerative ring resonator remains either conditionally stable or marginally unstable when operating the laser at powers that induce thermal lenses in optical elements inside the regenerative ring resonator.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 29, 2016
    Assignee: Cymer, LLC
    Inventors: Hong Ye, Richard L. Sandstrom, Rostislav Rokitski, Daniel J. W. Brown, Robert J. Rafac
  • Patent number: RE46059
    Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: July 5, 2016
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida
  • Patent number: RE46098
    Abstract: An illumination system generating light having at least one wavelength within 200 nm a plurality of nano-sized structures (e.g., voids). The optical fiber coupled to the light source. The light diffusing optical fiber has a core and a cladding. The plurality of nano-sized structures is situated either within said core or at a core-cladding boundary. The optical fiber also includes an outer surface. The optical fiber is configured to scatter guided light via the nano-sized structures away from the core and through the outer surface, to form a light-source fiber portion having a length that emits substantially uniform radiation over its length, said fiber having a scattering-induced attenuation greater than 50 dB/km for the wavelength(s) within 200 nm to 2000 nm range.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: August 9, 2016
    Assignee: Corning Incorporated
    Inventors: Scott Robertson Bickham, Dana Craig Bookbinder, Edward John Fewkes, Stephan Lvovich Logunov
  • Patent number: RE46122
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: RE46203
    Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 15, 2016
    Assignee: Floadia Corporation
    Inventors: Yutaka Shinagawa, Hideo Kasai, Yasuhiro Taniguchi
  • Patent number: RE46204
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
  • Patent number: RE46271
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: RE46303
    Abstract: A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate; filling the isolation region recess with an insulating material to form an isolation region; removing the block mask to expose a remaining plurality of dummy gates; and performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: RE46311
    Abstract: According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusuke Kawaguchi
  • Patent number: RE46325
    Abstract: An electrically powered light source including a light emitting diode (LED) having variable chromaticity, which is adapted for use in a dental operatory. A dental operatory lamp includes a thermally conductive housing having a front directed toward the operating area and a rear away from the operating area; a generally elliptical reflector located on the rear of the thermally conductive housing; at least one heat pipe; a plurality of color LEDs projecting light toward the elliptical reflector, the plurality of LEDs being in thermal contact with the at least one heat pipe; and an optical light guide for combining light from said LEDs. Another embodiment of the lamp includes at least two user selectable light spectra, one of said spectra providing white light with color temperature in the range 4000° K-6000° K and one spectra having reduced output in the wavelength range 400-500 nm.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: February 28, 2017
    Assignee: Kavo Dental Technologies, LLC
    Inventors: Jamie Swayne, H. Thomas Lockamy, Nabil Dagher, Wei Li, Joe Bria, Robert St. Louis, John Helgesen, Ted Von Badinski, Tom Benfeld, Austin Unsworth, Nathan Hemmer, Jason W. Spencer, Daniel B. Manglicmot
  • Patent number: RE46335
    Abstract: Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: March 7, 2017
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo, Hagop Nazarian
  • Patent number: RE46339
    Abstract: The present invention provides a method for plasma dicing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing a work piece onto the work piece support, said work piece having a support film, a frame and the substrate; loading the work piece onto the work piece support; applying a tensional force to the support film; clamping the work piece to the work piece support; generating a plasma using the plasma source; and etching the work piece using the generated plasma.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 14, 2017
    Assignee: Plasma-Therm LLC
    Inventors: Rich Gauldin, Chris Johnson, David Johnson, Linnell Martinez, David Pays-Volard, Russell Westerman, Gordon Grivna
  • Patent number: RE46389
    Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juwan Lim, Sungkweon Baek, Kwangmin Park, Seungjae Baik, Kihyun Hwang
  • Patent number: RE46390
    Abstract: According to the embodiments, a distribution of a recess portion shape is calculated based on a result obtained by measuring the recess portion shape of a first projection and recess pattern formed on a surface of a template. Next, a distribution of an application amount of a curing agent to a processing target layer is calculated based on the distribution of the recess portion shape, and the curing agent is applied to the processing target layer based on this distribution of the application amount of the curing agent. Next, a second projection and recess pattern is formed by transferring the first projection and recess pattern onto the curing agent by causing the curing agent to cure in a state where the first projection and recess pattern is in contact with the curing agent.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masafumi Asano, Ryoichi Inanami, Masayuki Hatano
  • Patent number: RE46418
    Abstract: An embodiment of a solid optical sky-sun diffuser, which comprises a transparent solid matrix embedding a dispersion of transparent nanoparticles having an average size d in the range 10 nm?d?240 nm; wherein: the ratio between the blue and red scattering optical densities ??Log [T(450 nm)]/Log [T(630 nm)] of said diffuser falls in the range 5???2.5, where T(?) is the Monochromatic Normalized Collinear Transmittance; in at least one propagation direction, said Monochromatic Normalized Collinear Transmittance is T(450 nm)?0.4; in at least one propagation direction said Monochromatic Normalized Collinear Transmittance is T(450 nm)?0.9, said propagation direction being the same or different from that at which said Monochromatic Normalized Collinear Transmittance is T(450 nm)?0.4.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: May 30, 2017
    Assignee: CoeLux S.r.l.
    Inventors: Paolo Di Trapani, Alessandro Averchi, Marta Cecilia Pigazzini