Abstract: A dual port random access memory device having a memory location which has interfaces for allowing at least two devices to access a given memory location. The memory location is subdivided into at least two portions. One of the portions is a source and one of the portions is a destination. A shadow updating mechanism is provided and connected to each of the memory location portions for allowing data stored in one of the portions to be copied into the other portion.

Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to read. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.