Abstract: A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

Abstract: In a computer system having a recording/ reproducing device in which a DVD-RAM or the like is used as a recording medium, the CPU and the memory allocates logical blocks and record blocks, in multiple units of a common block for data to be written on a recording medium. The common blocks have a size of the least common multiple of the size of logic block and the size of record block, and the front of the allocated logical blocks coincides with the front of the allocated record blocks. The data is recorded on the recording medium by the recording/reproducing device. Hence, the data can be recorded in the most desirable manner even if the logical blocks and the record blocks defer in size.

Abstract: A disk storage system with a RAID architecture, where the disk memory has N units of disks, includes a control unit to write data to the N units of disks or read data therefrom based on instructions from a host equipment, a volatile memory connected to the control unit, and a non-volatile memory connected to the control unit. The volatile memory includes a time stamp memory and a conversion map. The non-volatile memory includes a write buffer, which has a capacity of N×K logical block data (N is a positive integer not less than 2 and K is an integer indicating the number of blocks), and a buffer management table. The control unit accumulates logical block data to be updated in the write buffer until the number of logical blocks reaches N×K−1. It generates logical address tag blocks, including time stamps stored in the time stamp memory and adds them to the N×K−1 logical blocks.

Abstract: A method used by a first memory controller to prevent deadlock of requests to a memory having a first memory line is disclosed. The method includes the steps of (1) receiving a first memory request for the first memory line from a first bus, (2) receiving a second memory request for the first memory line from a second bus, (3) propagating the first memory request through to the second bus after the second memory request receiving step, (4) processing the second memory request by storing a first modified copy of the first memory line in the first memory controller, and (5) processing the first memory request by (a) storing a second modified copy of the first memory line in the first memory controller, and (b) transferring the second modified copy of the first memory line to a caching agent in order to satisfy the first memory request.

Abstract: A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line.

Abstract: In the manufacture of microcomputers, the output of either of two memory capacity select circuits is selected using a mask that is used for selecting data of a mask ROM, then the selected output is used to change the address space in which a built-in ROM is effective, and the space in which an external address corresponding to the storage capacity of the built-in ROM is effective is switched, whereby at least two kinds of storage capacities of the built-in memory and spaces in which external addresses corresponding thereto are effective can be selected.

Abstract: A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory ("ROM") in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.