Abstract: A processor has an execution unit that includes an arithmetic-logic-unit (ALU). Logic instructions are executed by a Boolean logic unit constructed around a 4:1 vectored mux. For Boolean logic instructions, the two operands are applied to the select control inputs of the vectored mux, while truth-table signals representing a truth-table for the Boolean operation being executed are applied to the data inputs of the vectored mux. Sign-extension of one of the operands can be performed by modifying the truth-table signals for an upper portion where the sign-extension occurs. Merge instructions are also executed on the vectored mux by reversing the connection of the operands to the vectored mux. The operands are applied to the select control inputs of the vectored mux for Boolean operations, but applied to the data inputs for merge operations. A mask is generated and applied to the select control inputs to select the correct portions of the first and second operands to generate the result of the merge operation.