Abstract: A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

Abstract: A flash translation layer with a rewind feature, and a method of operation. In some embodiments, the method includes: receiving, by a storage device, a first write command, for a first logical address; performing, by the storage device, a write to flash memory at a first physical address, corresponding to the first logical address; receiving, by the storage device, a first bookmarking command, for the first logical address; receiving, by the storage device, a second write command, for the first logical address; performing, by the storage device, a write to flash memory at a second physical address, corresponding to the first logical address; receiving, by the storage device, a first rewind command, for the first logical address; receiving, by the storage device, a read command, for the first logical address; and retrieving, by the storage device, in response to the read command, data from the first physical address.

Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.

Abstract: Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory. The controller is configured to specify a partition format of a predetermined partition included in the non-volatile memory based on master boot record information stored in the non-volatile memory. The controller is configured to specify a file system that manages the predetermined partition. The controller is configured to specify logically erased first data and physically erase the first data when logical erasure of data in the predetermined partition is detected by a method consistent with the specified file system.

Abstract: A method for aborting a command for PCIe based NVMe SSD includes receiving an abort command in an Admin submission queue to abort a target command present in an I/O submission queue of host or in an I/O queue of the NVMe SSD and updating a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command. The abort command includes a slot of the target command to be aborted. Thereafter, the method includes placing the abort command into an Admin queue of the NVMe SSD and executing the abort command using the slot of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted. The method further includes updating a head doorbell of the doorbell registers of the NVMe SSD and updating the abort command in an Admin completion queue of the host.

Abstract: According to one embodiment, a computing device executes an application including processing of inputting information from a nonvolatile memory unit and outputting information to the nonvolatile memory unit. The computing device includes a processing unit. The processing unit executes processing of receiving an I/O request to the nonvolatile memory unit from the application and generating one or more control commands for controlling the nonvolatile memory unit based on the I/O request. The processing unit executes processing of acquiring authorization information from a server. The processing unit executes processing of inserting or associating the acquired authorization information into or with the I/O request or the one or more control commands.

Abstract: A secure memory card includes a non-volatile memory device for storing data, which includes a specific address and a regular address different from the first specific address; a secure element for conducting a securing operation; and a non-volatile memory controller in communication with the non-volatile memory device and the secure element, adapted to receive a command from a host. The non-volatile memory controller interacts with the secure element to conduct the securing operation in response to the command from the host if the command from the host is secure-element control command. The secure-element control command is a single command taking a single instruction cycle and corresponds to the specific address. The non-volatile memory controller interacts with the non-volatile memory device while having no interaction with the secure element in response to the command from the host if the command from the host is a non-secure-element control command corresponding to the regular address.

Abstract: A computing system includes a storage system configured to store data, and a host configured to compress a data block of a preset size loaded to a memory, generate a merged block of the preset size by merging a compressed block corresponding to the data block, an identifier of a node block referring the data block, and an offset indicating an index of the data block among at least one data block referred by the node block, and provide the merged block to the storage system.

Abstract: A key-value (KV) storage method and apparatus, the method including receiving a write request, where the write request is associated with writing a first key and a first value, storing the first key in a first memory chip of a solid state drive (SSD), and storing the first value in a second memory chip of the SSD, where an erase count of the first memory chip is less than an erase count of the second memory chip, and creating a mapping relationship between the first key, a physical address of the first key, and a physical address of the first value, where the physical address of the first key indicates that the first key is stored in storage space of the first memory chip, and where the physical address of the first value indicates that the first value is stored in storage space of the second memory chip.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: Integrated circuit device having a processor module (2) in communication with a cache memory module (3, 4), and one or more memory control modules (6, 8, 10) each arranged to interface with an associated storage memory unit (5, 7, 9). An authentication module (15) is provided in communication with the memory control modules (6, 8, 10) and the cache memory modules (3, 4). The authentication module (15) is arranged to generate and store a hardware based secure key, read a predetermined set of data from the associated storage memory units (5, 7, 9), and an associated stored hash value, calculate a hash value of the predetermined set of data using the hardware based secure key; and store the predetermined set of data in the cache memory module (3, 4) only if the calculated hash value corresponds to the associated stored hash value.

Abstract: Systems and methods for performing single I/O writes are provided. According to one embodiment, responsive to receipt of a write operation from a client by a file system layer of a node of a distributed storage system and a data payload of the operation having been determined to meet a compressibility threshold, an intermediate storage layer of the node logically interposed between the file system layer and a block storage media is caused to perform a single input/output (I/O) write operation that persists the compressed data payload and corresponding metadata to support asynchronous journaling of the write operation. The single I/O write operation coupled with the use of a new pool file that maintains a list of available blocks for single I/O write operations and a modified node crash recovery approach allows the write operation to be acknowledged to the client while the journaling is performed asynchronously.

Abstract: A system can use non-volatile solid state drives (SSDs) to provide storage. The SSDs can implement internal log structured systems (LSSs). A reversible write operation can be serviced by an SSD to write first data to an SSD logical address. The reversible write operation can update the SSD logical address to store the first data rather than old data stored at the SSD logical address prior to servicing the reversible write operation. The old data can be stored at an SSD physical address and mapping information indicates the SSD logical address is mapped to the SSD physical address. Servicing the reversible write operation can include: retaining the mapping information and the old data; and adding second mapping information that maps the SSD logical address to a second SSD physical address storing the first data. A subsequent read operation can read the old data using the retained mapping information.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to program key value (KV) pair data to the memory device, where the KV pair data includes a key and a value, analyze the key, and generate metadata based on the analyzing. The controller is further configured to generate a metadata index for a plurality of KV pair data, where the metadata index value corresponds to a similarity or a difference between a first key and a second key, and cluster generated metadata based on the metadata index. The controller is further configured to receive a read command for the KV pair data, analyze the generated metadata of the KV pair data, generate a predicted next key, and use read look ahead (RLA) to read a predicted next KV pair data based on the predicted next key.

Abstract: A system and method for performing replication using mediums. A snapshot ‘S’ is selected for replication, and the anchor medium ‘M’ of S is identified. The replica storage array ‘R’ to which M is being replicated determines a list of medium extents which are available. R sends this list to an original storage array ‘O’ and O generates a list of medium extents which need to be sent to R. Only those medium extents corresponding to M which R does not already have will be sent from O to R. Also, R can obtain medium extents from other source storage arrays during the replication process.

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

Abstract: A control apparatus includes a first accepting unit accepting multiple requests from a host controller, a first transmission unit transmitting the multiple host controller requests to a storage upon acceptance, from the storage, of a transmission request for the multiple requests, a second accepting unit accepting the multiple host controller requests and accepting a response to each host controller request from the storage, a first storing unit storing the multiple host controller requests and storing the accepted response to each host controller request, the accepting performed by the second accepting unit, and a control unit causing, upon acceptance of an error as the response to a first host controller request, among the multiple host controller requests, the first storing unit to store the same request as the first host controller request.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.