Abstract: A method, computer program product, and computing system for processing an input/output (IO) request on a storage processor within a storage system. An entry is generated in a transactional journal for the IO request. A copy of the entry is stored in the transactional journal in a dedicated data container in volatile memory of the storage processor. In response to processing a subsequent IO request associated with the entry, the entry is at least partially overwritten in the dedicated data container.

Abstract: Systems and methods for identifying regions of a memory device are disclosed. A storage device comprises a first storage medium, a second storage medium, and a processor configured to: identify a first memory address; identify a first region of the first storage medium based on the first memory address; identify a first criterion associated with the first memory address; based on identification of the first criterion, identify a portion of the first region based on the first memory address; identify a second criterion associated with the portion; and retrieve data associated with the portion from the first storage medium to the second storage medium based on identification of the second criterion.

Abstract: A computer-implemented method for cost and carbon aware large language model (LLM) cache management is disclosed. The method includes: determining whether a prompt matching an input prompt exists in a plurality of prompts stored in a cache memory; upon determining that the prompt matching the input prompt exists in the cache memory, returning a response associated with the prompt from the cache memory; otherwise, (a) invoking the LLM and returning a response generated by the LLM, (b) updating the cache memory with the input prompt and the associated response obtained from the LLM as an entry in the cache memory, (c) estimating an operational cost and a carbon cost associated with generating the response to the input prompt, (d) fetching data associated with the LLM, and (e) updating the operational cost, the carbon cost and the data associated with the LLM as metadata of the entry in the cache memory.

Abstract: The present technology enhances workload management of data storage systems by using an internal copy function and/or a zone-append technology. The internal copy function is used, e.g., in merge operations to move data between locations on a disk without using off-disk resources (e.g., processing or memory of a CPU). Zone-append technology uses nameless writes (e.g., write instruction without an assigned destination address on the disk) to combine IO units from different threads to be written to a common zone of a disk (e.g., a shingled magnetic recording (SMR) disk). Sequential addresses are assigned to IO units from different threads based on their order in the write queue, reducing the latency and seek time typically associated with random writes. The zone-append technology, e.g., uses sequential write operations within specified zones, allowing the disk to determine the actual write location and to report post-write logical block addresses (LBAs).

Abstract: Examples of the present disclosure provide a memory system, a memory controller, a control method, and a storage medium. The method includes: sending a first command phase of a first command, sending a second command in idle time of the first command, and sending a second command phase of the first command when the idle time of the first command expires.

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Abstract: A memory system may include a memory media and a controller. The controller may receive from a host a first read command which requests to read target data stored in a target address of the memory media, read the target data from the memory media, store the read target data in a buffer, generate a first response message to the first read command on the basis of the read target data, receive, after receiving the first read command, from the host a second read command which requests to read the target data, and generate a second response message to the second read command on the basis of the target data stored in the buffer.

Abstract: A storage node configuration method includes obtaining service requirement information, where the service requirement information includes a burst access moment, a burst access bandwidth, or burst access duration of a computing node for a storage node; determining target configuration information based on the service requirement information, where the target configuration information is used to configure a peak bandwidth and peak bandwidth duration that are of the storage node; and sending the target configuration information to the storage node.

Abstract: An electronic device may include: a processor including a first core and a second core, the first core and the second core being configured to execute a process; and a main memory configured to store a page table corresponding to the process. The first core includes: a first translation lookaside buffer (TLB) configured to store a first portion of the page table; a page table walker configured to perform a page table walk operation to look up the page table; and a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core. The second core includes a second TLB configured to store a second portion of the page table.

Abstract: A device may include a device memory, and a device functionality circuit, wherein at least a portion of the device functionality circuit may be capable of accessing at least a portion of the device memory, and a control circuit configured to provide information, wherein the information may indicate that the at least a portion of the device functionality circuit may be capable of accessing the at least a portion of the device memory. Additionally, or alternatively, the control circuit may be configured to receive at least one request, and perform, based on the at least one request, a configuration operation, wherein the configuration operation may include configuring at least a portion of the device memory to be accessed by the at least a portion of the device functionality circuit.

Abstract: A module identifier and a request address associated with an access request are received at a host memory buffer (HMB) access module in a solid-state drive (SSD) system. A translated address is determined based at least in part on the module identifier and the request address, including by accessing at least one translation table that stores address mappings between (1) a plurality of processors in the SSD system and (2) a host memory buffer; each processor in the plurality of processors has a non-overlapping memory space in the host memory buffer. The access request is performed at a host interface, including by accessing the host memory buffer using the translated address, wherein the host memory buffer is located in host memory that is external to the SSD system.

Abstract: Data processing method and apparatus, an electronic device, and a storage medium are disclosed, which is in the fields of artificial intelligence, such as distributed storage and cloud computing.

Abstract: A host I/O (Input/Output) request workload including block I/O requests and file I/O requests is received by a data storage system. A file I/O share of the host I/O request workload is detected. The file I/O share of the host I/O request workload indicates a proportion of the host I/O request workload that consists of file I/O requests. The amount of block I/O request processing assigned to an individual shared processor core is modified based on the file I/O share of the host I/O request workload. The shared processor core is shared between a file I/O request processing component of the data storage system and a block I/O request processing component of the data storage system.

Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associated with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

Abstract: Disclosed is a method of operating a storage device including a plurality of chips, the method including: receiving a write request of stream data; checking a program status or a stream queue of each of the plurality of chips; based on a determination that there is at least one chip in a ready state with an empty stream queue among the plurality of chips, allocating the stream data to the at least one chip in the ready state; and based on a determination that there is no chip in the ready state with the empty stream queue among the plurality of chips, allocating the stream data to at least one chip based on a number of streams in a stream queue among the plurality of chips.

Abstract: This disclosure is directed to a system for high efficiency storage in high capacity non-volatile solid state applications. The system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including receiving a request to program data, storing the data by default in a first type of storage with multi-level memory cells having a first number of levels, and bypassing a second type of storage with fewer levels. Upon detecting a condition, the processing device transfers the data to a third type of storage with a greater number of levels than the first type. This method optimizes storage efficiency and performance by dynamically managing data storage based on the portion of user logical block addresses that contain user data.

Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.

Abstract: A storage device includes a storage controller and a non-volatile memory including a first memory region including first memory cells having a first data retention time and a second memory region including second memory cells having a second data retention time that is shorter than the first data retention time. Based on an erase request being received from a host in a first operation mode, the storage controller determines whether to switch from the first operation mode to a second operation mode. The storage controller programs program data in a memory region selected from the first memory region and the second memory region in the first operation mode, and the storage controller programs the program data in only the first memory region in the second operation mode.

Abstract: A solid-state drive capable of executing a read operation concurrent with executing an erase operation, and a method of executing a read operation concurrent with executing an erase operation in a solid-state drive. A first portion of stored data that has been predicted (based on, e.g., recency of storage, frequency of access, relevancy to other operations) to be the subject of a potential read request is identified, and that data is copied to a page buffer. Subsequently, while executing an erase operation involving second data, an actual read request is received involving a third portion of stored data. The read request is executed without suspending the erase operation when the third portion of stored data is included in the first portion of stored data in the page buffer, and the erase operation is suspended to execute the read operation when the third portion of stored data is not included.

Abstract: A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.