Patents Examined by Jane Wei
  • Patent number: 9734333
    Abstract: Methods of detecting malicious code injected into memory of a computer system are disclosed. The memory injection detection methods may include enumerating memory regions of an address space in memory of computer system to create memory region address information. The memory region address information may be compared to loaded module address information to facilitate detection of malicious code memory injection.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 15, 2017
    Assignee: HEAT SOFTWARE USA INC.
    Inventor: Daniel Teal
  • Patent number: 9710193
    Abstract: A method of detecting a rewritable non-volatile memory module is provided. The method includes setting an output voltage of a write protect pin of a memory interface as a first logic level, giving a read status command and receiving a first status message. The method further includes determining whether a corresponding bit data in the first status message conforms to a status corresponding to the first logic level; and if yes, identifying that the rewritable non-volatile memory module has connected to the memory interface.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: July 18, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Patent number: 9684625
    Abstract: When a process is swapped out of memory, a record of the sharable memory pages of the process is maintained. The sharable memory pages can then be repurposed. When the process is subsequently swapped back into memory, concurrently with the process running the sharable memory pages of the process are prefetched. If during this prefetching the process requests a memory page that is not currently in physical memory, a high priority I/O request is issued for that memory page. The high priority I/O request is placed at the front of an I/O queue, so the high priority I/O request is processed before the pending prefetch requests.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 20, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy M. Bak, Mehmet Iyigun
  • Patent number: 9652373
    Abstract: Embodiments relate to adaptive memory apportioning. An aspect includes, statistics captured for a plurality of elements of a partitioned linear address space. Each addressable location is an element in the address space. Subspaces of the partitioned linear address space are rated based on captured statistics of at least one element. The subspaces are differentiated, based on the frequency of access, as being of lesser and greater significance. The boundaries that separate the subspaces are altered so as to effect coarser granularity in the subspaces determined to have the lesser significance and finer granularity in the subspaces determined to have the greater significance.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Clement L. Dickey
  • Patent number: 9645924
    Abstract: A computer processor determines an over-provisioning ratio and a host write pattern. The computer processor determines a write amplification target based on the host write pattern and the over-provisioning ratio. The computer processor determines a staleness threshold, wherein the staleness threshold corresponds to a ratio of valid pages of a block to total pages of the block. The computer processor erases a first block having a staleness which exceeds the staleness threshold.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Aaron D. Fry, Samuel K. Ingram, Lincoln T. Simmons
  • Patent number: 9594686
    Abstract: In one general aspect, a computer-readable storage medium can be configured to store instructions that when executed cause one or more processors to perform a process. The process can include establishing at least a portion of a communication link between a computing device and a storage system operating within a cloud environment. The process can include accessing a user interface including a listing of files representing a plurality of files where at least a first portion of the plurality of files are stored in a local memory of the computing device and a second portion of the plurality of files are stored in the storage system.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 14, 2017
    Assignee: Google Inc.
    Inventors: Joshua Woodward, Kazuhiro Inaba, Kenneth Brian Moore, Achuith Bhandarkar, Kokkuan Tan
  • Patent number: 9569310
    Abstract: Described herein is a system and method for a scalable crash-consistent snapshot operation. Write requests may be received from an application and a snapshot creation request may further be received. Write requests received before the snapshot creation request may be associated with pre-snapshot tags and write requests received after the snapshot creation request may be associated with post-snapshot tags. Furthermore, in response to the snapshot creation request, logical interfaces may begin to be switched from a pre-snapshot configuration to a post-snapshot configuration. The snapshot may then be created based on the pre-snapshot write requests and the post-snapshot write requests may be suspended until the logical interfaces have switched configuration.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 14, 2017
    Assignee: NetApp, Inc.
    Inventors: Bipul Raj, Gaurav Makkar
  • Patent number: 9563385
    Abstract: Methods and apparatus for profile-guided preloading for virtualized resources are described. A block-level storage volume whose contents are to be populated via data transfers from a repository service is programmatically attached to a compute instance. An indication of data transfers from the repository to a block storage service implementing the volume is obtained, corresponding to a particular phase of program execution at the compute instance. A storage profile is generated, based at least in part on the indication of data transfers. The storage profile is subsequently used to pre-load data from the repository service on behalf of other compute instances.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 7, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Marcin Piotr Kowalski, David R. Richardson, James Alfred Gordon Greenfield, Jacobus Johannes Nicolaas Van Der Merwe, Matthew James Eddey, Christopher Richard Jacques De Kadt, Peter Nicholas Desantis
  • Patent number: 9519581
    Abstract: Techniques for enabling integration between a storage system and a host system that performs write-back caching are provided. In one embodiment, the host system can transmit to the storage system a command indicating that the host system intends to cache, in a write-back cache, writes directed to a range of logical block addresses (LBAs). The host system can further receive from the storage system a response indicating whether the command is accepted or rejected. If the command is accepted, the host system can initiate the caching of writes in the write-back cache.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 13, 2016
    Assignee: VMware, Inc.
    Inventors: Andrew Banta, Erik Cota-Robles
  • Patent number: 9489321
    Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 8, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James M. O'Connor, Niladrish Chatterjee, Nuwan S. Jayasena, Gabriel H. Loh
  • Patent number: 9460028
    Abstract: Data migration is performed in a cluster of host computers each using a mechanism associating data with a source LUN. During a synchronization operation the contents of the source LUN are copied to the target LUN while ongoing normal source LUN writes are cloned to the target LUN. A datapath component of an agent coordinates the writes at the target LUN to maintain data consistency. Upon completion of synchronization, each host stops the write cloning and disables access to the source LUN, in conjunction with a modification of the mechanism to newly associate the data with the target LUN. Depending on the type of mechanism and system, the modification may be done either disruptively or non-disruptively, i.e., with or without stopping normal operation of software of the host computers.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 4, 2016
    Assignee: EMC Corporation
    Inventors: Helen S. Raizen, Assaf Natanzon
  • Patent number: 9444905
    Abstract: Provided are a computer program product, system, and method for allocating network bandwidth to prefetch requests to prefetch data from a remote storage to cache in a local storage. A determination is made of access rates for applications accessing a plurality of files, wherein the access rate is based on a rate of application access of the file over a period of time. A determination is made of an access rate weight for each of the files based on the access rates of the plurality of files. The determined access rate weight for each of the files is used to determine network bandwidth to assign to access the files from the remote storage to store in the local storage.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shah Mohammad R. Islam, John T. Olson, Sandeep R. Patil, Riyazahamad M. Shiraguppi
  • Patent number: 9436595
    Abstract: A data storage device includes a plurality of flash memory devices. A memory controller is configured to receive a request from a host computing device to write a first logical block of application data to the data storage device, write the first logical block to a data buffer, wherein a size of the data buffer is larger than the logical block and may store multiple logical blocks, write one or more logical blocks of garbage-collected data to the data buffer, and write the logical blocks in the data buffer to the data storage device when the data buffer becomes full. The data buffer written to the data storage device includes at least one logical block of application data and at least one logical block of garbage-collected data. In an alternative implementation, garbage-collected data may be written to the data buffer upon expiration of a timer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 6, 2016
    Assignee: Google Inc.
    Inventors: Manuel Enrique Benitez, Monish Shah
  • Patent number: 9298375
    Abstract: Techniques are disclosed for reducing perceived read latency. Upon receiving a read request with a scatter-gather array from a guest operating system running on a virtual machine (VM), an early read return virtualization (ERRV) component of a virtual machine monitor fills the scatter-gather array with data from a cache and data retrieved via input-output requests (IOs) to media. The ERRV component is configured to return the read request before all IOs have completed based on a predefined policy. Prior to returning the read, the ERRV component may unmap unfilled pages of the scatter-gather array until data for the unmapped pages becomes available when IOs to the external media complete. Later accesses to unmapped pages will generate page faults, which are handled by stunning the VMs from which the access requests originated until, e.g., all elements of the SG array are filled and all pages of the SG array are mapped.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 29, 2016
    Assignee: VMware, Inc.
    Inventors: Erik Cota-Robles, Thomas A. Phelan
  • Patent number: 9239790
    Abstract: Techniques for evicting cached files may be realized as a method including: maintaining a file system cache storing selected files from a file storage; for files that are above a threshold size, selectively storing chunks of the files; for each file that is stored, associating an access bit and a size bit with that file; for each file that is stored selectively as file chunks, associating an access bitmap to the file having an access bit associated with each file chunk; when a file is accessed, setting the access bit associated with the file and file chunk to indicate recent access; at set intervals, periodically clearing the access bits to not indicate recent access; and carrying out a cache eviction process comprising evicting at least one file or file chunk associated with an access bit that does not indicate recent access.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 19, 2016
    Assignee: Symantec Corporation
    Inventors: Anindya Banerjee, Ryan R. Lefevre
  • Patent number: 9239682
    Abstract: An I/O hint framework is provided. In one embodiment, a computer system can receive an I/O command originating from a virtual machine (VM), where the I/O command identifies a data block of a virtual disk. The computer system can further extract hint metadata from the I/O command, where the hint metadata includes one or more characteristics of the data block that are relevant for determining how to cache the data block in a flash storage-based cache. The computer system can then make the hint metadata available to a caching module configured to manage the flash storage-based cache.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: January 19, 2016
    Assignee: VMware, Inc.
    Inventors: Deng Liu, Thomas A. Phelan, Li Zhou, Ramkumar Vadivelu, Sandeep Uttamchandani
  • Patent number: 9195465
    Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 24, 2015
    Assignee: Intel Corporation
    Inventors: Varun K. Mohandru, Fernando Latorre, Li-Gao Zei, Allan D. Knies, Rami May, Lutz Naethke