Abstract: Systems and methods are provided for phased array passband calibration, which permits repeated calibration of the antenna system in the field without a moving far field sensor. An implementation includes an equalization filter coupled to a phased array feed; a calibration probe disposed to couple with an antenna array to transfer radio frequency (RF) energy; a database of probe-to-far-field (FF) transforms having a probe-to-FF transform for each of a plurality of incidence angles; a calibration component operable to: receive calibration probe measurements for a plurality of frequencies; and determine a calculated phased array passband response for at least a first incidence angle, based at least on the calibration probe measurements and a probe-to-FF transform for the first incidence angle; and a filter generation component operable to generate a tuning configuration for the equalization filter, based at least on the calculated phased array passband response.

Abstract: The present disclosure relates to an apparatus and a method for supporting an improved communication speed in a wireless power transmission system. In such present specification, provided is the method comprising the steps of: transmitting at least one data packet to a wireless power reception apparatus; receiving, from the wireless power reception apparatus, a first request packet requesting a change in a communication speed of the wireless power transmission apparatus; and changing the communication speed of the wireless power transmission apparatus on the basis of the first request packet, and transmitting, at the changed communication speed, a first response packet in response to the first request packet to the wireless power reception apparatus.

Abstract: A receiver for OFDM subcarriers has a first mode and a second mode. In the first mode, a tunable system clock is output at a nominal frequency, and in the second mode, the tunable system clock is offset so that a harmonic of the tunable system clock coincides with a particular OFDM subcarrier. The tunable system clock is coupled to a programmable modem PLL clock generator which generates clocks for an A/D converter coupled to a baseband processor which is also coupled to the programmable modem PLL clock generator. The programmable modem PLL clock generator is programmed to maintain a constant output frequency of each output in the first mode and the second mode.

Abstract: A system and method for providing multi-input multi-output (MIMO) feeder links for a multibeam satellite system. The method includes configuring a X×Y MIMO antenna system using X-antennae having dominant line-of-sight (LoS) of Y-antennae; transmitting, simultaneously, a Tx signal as X Tx signals on a MIMO channel with the X-antennae; receiving the X Tx signals on the MIMO channel with the Y-antennae as Y Rx signals, wherein each of the Y-antennae generate one of the Y Rx signals; and ground-interference processing the X Tx signals or the Y Rx signals to recover the Tx signal; satellite-interference processing the X Tx signals or the Y Rx signals to recover the Tx signal. In the method, the ground interference processing includes countermeasures as either pre-interference processing when the X-antennae are disposed on a ground or post-interference processing when the X-antennae are disposed in a Geosynchronous orbit satellite.

Abstract: In mobile communications networks, requirements on signal distortion may be fulfilled at a lower bit rate, or alternatively quantization noise be reduced for a given bit rate, by including fractional exponent bits in a block floating point format. One or more fractional exponent bits may apply to all samples in the block. Alternatively, fractional bits may apply to sub-blocks within the block. The optimal number of fractional bits depends on the number of samples in the block.

Abstract: A 10BASE-T1S PHY method and apparatus are provided for receiving an analog MDI signal conveying DME-encoded data at a receiver comparator to generate a digital output signal, processing the digital output signal using a pulse encoder to generate a pulse-coded output signal with pulses generated at each rising or falling transition in the digital output signal, processing the pulse-coded output signal with an output driver to generate a pulse-coded driver output signal that is transmitted to a receiver interface pin RX, processing the pulse-coded driver output signal with an input comparator to generate a pulse-coded comparator output signal, processing the pulse-coded comparator output signal using a pulse decoder to generate a DME-encoded PMA input signal in which timing asymmetries caused by processing at the receiver comparator and/or output driver have been eliminated, and then processing DME-encoded PMA input signal at a digital PHY circuit in the Ethernet PHY.

Abstract: Embodiments herein describe assigning different linearity operating points of a front end of a radio to groups of user devices when transmitting data using OFDMA. That is, when transmitting a PPDU to a first group of user devices, an access point (AP) may set the front end of the radio to a lower linearity operating point than when transmitting a PPDU to a second group of user devices. Using a higher linearity operating point can increase the data rate used to transmit the PPDU—e.g., the AP can use a higher modulation coding scheme (MCS). This can reduce the time the PPDUs have to wait in a queue before being transmitted.

Abstract: A receiving device includes a reception unit 10 that samples a signal to be measured a transmitted from a DUT 2 and acquires a sample signal d; an FFT processing unit 21 that performs an FFT process by multiplying the sample signal; a signal length calculation unit 31 that calculates a signal length of the signal to be measured from the sample signal; a comparing unit 33 that compares the calculated signal length of the signal to be measured with a first FFT length conforming to a communication standard; and an FFT length setting unit 34 that, when as a result of the comparison by the comparing unit, the signal length is shorter than the first FFT length, sets a second FFT length shorter than the signal length of the signal to be measured, as the FFT length of the FFT process by the FFT processing unit.

Abstract: A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Abstract: An orbiting multiple access transceiver communicates with terrestrial mobile stations which are also capable of communicating with terrestrial base stations. The multiple access transceiver is configured to sample a signal when a terrestrial mobile station of interest is not transmitting to produce a sample signal. The sample signal may be processed to produce an out-of-phase signal that may be applied to a signal when the terrestrial mobile station of interest is transmitting to produce a clearer signal from the terrestrial mobile station of interest.

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Abstract: A communication apparatus of the present disclosure includes a receiver which, in operation, receives a signal that includes a non-legacy preamble and a data field, the non-legacy preamble comprising a first field for indicating a number of spatial streams (Nss) in the data field and a second field for indicating one of a plurality of modulation and coding schemes (MCSs), wherein two or more frequency diversity transmission schemes are supported and one of the two or more frequency diversity transmission schemes is applied based on a value of the Nss; and circuitry which, in operation, decodes the signal.

Abstract: Techniques are disclosed relating to generating and receiving radio frames with multiple portions that have different target geographic areas. A data frame may include a first partition that includes a physical layer encoding of first data to be transmitted in a first geographic area, where the first geographic area is defined by a first threshold distance from the one or more transmitters. The data frame may include a second that includes a physical layer encoding of second data to be transmitted in a second geographic area, where the second geographic area is defined by a second, greater threshold distance from the one or more transmitters.

Abstract: Disclosed are techniques for computing and reporting a relevance metric for a positioning beacon beam. In an aspect, a first node receives, from a second node, a plurality of beams, determines a relevance metric for each of one or more beams of interest from the plurality of beams, wherein the relevance metric for each beam of the one or more beams of interest is based on a time of arrival at the first node of the beam and a signal strength of the beam, and sends, to the second node, a report identifying each of the one or more beams of interest and including the relevance metric for each of the one or more beams of interest.

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Abstract: A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: A system and method for generating a high entropy (HE) constant-envelope Gaussian minimum shift keying (GMSK) modulated signal with suppressed cyclostationary features is disclosed. In embodiments, the system includes a primary GMSK modulator for generating an initial GMSK signal based on a received data stream for transmission. The system includes a sequence of secondary GMSK modulators for generating a sequence secondary GMSK signals based on pseudorandom number sequences based on distinct chip rates. The initial GMSK signal is multiplied by the first secondary GMSK signal to generate an initial composite GMSK signal, which is sequentially multiplied by each subsequent secondary GMSK signal until a final composite GMSK signal is achieved, the final composite GMSK signal being a HE-GMSK constant-envelope signal with suppression of cyclic and cyclostationary features that might otherwise cause detection or interception of the signal.