Patents Examined by Jasmine Song
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Patent number: 9003164Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.Type: GrantFiled: March 21, 2014Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
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Patent number: 9003120Abstract: Embodiments of the present invention disclose a method and an apparatuses for querying for and traversing a virtual memory area. The method includes: determining whether a virtual memory area (vma) corresponding to a query address is in an adjacent range of a cached vma, and if the vma corresponding to the query address is in the adjacent range of the cached vma, querying for the vma by using a thread on a node of a threaded red-black tree. Since an adjacent range of the cached vma can always be determined, the hit rate of accessing the cache is improved, and the time complexity of implementing the whole vma traversal is O(n), thereby improving vma query efficiency.Type: GrantFiled: February 27, 2014Date of Patent: April 7, 2015Assignee: Huawei Technologies Co., Ltd.Inventor: Qiang Huang
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Patent number: 9003160Abstract: According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.Type: GrantFiled: August 3, 2012Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime H. Moreno, Ravi Nair
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Patent number: 8996843Abstract: A method for assigning data in a plurality of physical storage resources for an information handling system is disclosed. The plurality of physical storage resources includes a first tier and a second tier with a lower performance and cost relative to capacity than the first tier. A tier manager hosted on the information handling system and in electronic communication with the plurality of physical storage resources is configured to: determine a seek distance value, operation rate, operation size value, and elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier.Type: GrantFiled: April 29, 2013Date of Patent: March 31, 2015Assignee: Dell Products L.P.Inventors: William Price Dawkins, Stephen Gouze Luning
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Patent number: 8996830Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for efficient backup using hashes One of the methods includes forming an image of a storage device, wherein contents of blocks of the storage device are restorable from the contents of blocks of the image. The method includes generating a first plurality of hash values, each hash value generated from contents of a block of the image. The method includes selecting a block of the storage device. The method includes generating a hash value from the contents of the selected block. The method includes determining whether the hash value occurs in the plurality of hash values. The method also includes generating an entry in the image in response to the determination.Type: GrantFiled: June 14, 2013Date of Patent: March 31, 2015Assignee: Acronis International GmbHInventors: Maxim V. Goldobin, Maxim V. Lyadvinsky, Serguei M. Beloussov, Alexander G. Tormasov, Yuri S. Per
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Patent number: 8984224Abstract: The present invention is directed to a method and software for managing the host-to-volume mappings of a SAN storage system. The host-to-volume mappings of the SAN storage system are represented in mapping configuration components. The active mapping configuration component represents the current host-to-volume mapping for the SAN storage system. Only one mapping configuration component is active at a time. The host-to-volume mappings of the SAN storage system are changed by deactivating the active mapping configuration component and activating an inactive mapping configuration component that represents a different mapping configuration, effecting a repartition, repurpose, disaster recovery, or other business activity. This can be a scheduled task or performed in an on-demand manner. The mapping configuration components are managed and controlled through the management component of the SAN storage system.Type: GrantFiled: January 22, 2014Date of Patent: March 17, 2015Assignee: NetApp, Inc.Inventors: Yanling Qi, Jason Sherman
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Patent number: 8984226Abstract: A method of load balancing can include segmenting data from a plurality of servers into usage patterns determined from accesses to the data. Items of the data can be cached in one or more servers of the plurality of servers according to the usage patterns. Each of the plurality of servers can be designated to cache items of the data of a particular usage pattern. A reference to an item of the data cached in one of the plurality of servers can be updated to specify the server of the plurality of servers within which the item is cached.Type: GrantFiled: June 24, 2011Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventor: Kenneth S. Sabir
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Patent number: 8984213Abstract: A method for managing a flash memory including a plurality of blocks is provided. Each block includes a plurality of sets of a first page and a second page configured in pair. In response to a request for writing target data into a target block, at least one cache block is selected from the blocks. The target data is then written into the first pages in the at least one cache block. When a write-back condition is established, the target data is written from the cache block back to the target block.Type: GrantFiled: November 21, 2012Date of Patent: March 17, 2015Assignee: MStar Semiconductor, Inc.Inventors: Chien-Hsiang Li, Tse-Wei Wang
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Patent number: 8984211Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.Type: GrantFiled: December 21, 2011Date of Patent: March 17, 2015Assignee: Hitachi, Ltd.Inventors: Tsukasa Shibayama, Akifumi Suzuki, Nobuhiro Maki, Junji Ogawa, Masayasu Asano
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Patent number: 8966189Abstract: To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published by another user, a local deviation is created, and when the modification is published, it is associated with an unambiguous sequence reference and the local deviation.Type: GrantFiled: March 16, 2012Date of Patent: February 24, 2015Assignee: Tekla CorporationInventor: Teemu Rantanen
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Patent number: 8966184Abstract: An apparatus, system, and method are disclosed for managing eviction of data. A grooming cost module determines a grooming cost for a selected region of a nonvolatile solid-state cache. The grooming cost includes a cost of evicting the selected region of the nonvolatile solid-state cache relative to other regions. A grooming candidate set module adds the selected region to a grooming candidate set in response to the grooming cost satisfying a grooming cost threshold. A low cost module selects a low cost region within the grooming candidate set. A groomer module recovers storage capacity of the low cost region.Type: GrantFiled: January 31, 2012Date of Patent: February 24, 2015Assignee: Intelligent Intellectual Property Holdings 2, LLC.Inventor: David Atkisson
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Patent number: 8966218Abstract: A method for predictively allocating space in a database system includes detecting an access request for a data set, evaluating a growth rate of the data set to determine a predicted increase in size of the data set, and in response dynamically altering an attribute of an allocation for the data set. Attributes altered include the size of volumes and the number of volumes comprising the data set. The method may include setting a flag indicating an instruction to rewrite the data set if the evaluation indicates that rewriting is needed to accommodate the predicted increase in size. The method may include rewriting the data set from a lower address space of a volume to a higher address space of the volume if the size of the data set is equal to or greater than an allocation increment of the upper address space. A corresponding apparatus and computer program product are also disclosed herein.Type: GrantFiled: July 1, 2010Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: David C. Reed, Max D. Smith
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Patent number: 8966182Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.Type: GrantFiled: February 8, 2011Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Giora Biran, Christoph Hagleitner, Timothy H. Heil, Russell D. Hoover, Jan Van Lunteren
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Patent number: 8954707Abstract: A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully.Type: GrantFiled: August 3, 2012Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Ahmed Gheith, Eric Van Hensbergen, James Xenidis
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Patent number: 8954700Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.Type: GrantFiled: August 2, 2012Date of Patent: February 10, 2015Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Satyanarayana Lakshmipathi Billa
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Patent number: 8954659Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.Type: GrantFiled: December 18, 2013Date of Patent: February 10, 2015Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Sadahiro Sugimoto, Akihiko Araki, Masayuki Yamamoto
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Patent number: 8949530Abstract: Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.Type: GrantFiled: August 2, 2011Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Mvv A. Krishna, Shaul Yifrach
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Patent number: 8935473Abstract: The present invention is a system and method for a portable memory device to access and acquire additional memory from a remote location by utilizing a network connection to access remote memory. A portable memory device comprising of software that can determine the location of data to be stored based on a criteria that governs whether data may be stored locally or remotely, may utilize a network, connected to one or several remote locations with available memory storage space, to access available memory and store data remotely.Type: GrantFiled: January 5, 2007Date of Patent: January 13, 2015Assignee: New DaneInventor: Jonathan Weizman
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Patent number: 8924672Abstract: Embodiments related to a processing unit and a first information storage are described and depicted. First information is provided from a first unit into a first information storage for performing a first operation of the processing unit. During the first operation of the processing unit second information is transferred between the processing unit and the first information storage. The first information storage comprises during the first operation of the processing unit an access protection for the first unit.Type: GrantFiled: February 8, 2011Date of Patent: December 30, 2014Assignee: Infineon Technologies AGInventors: Karl Herz, Joerg Syassen
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Patent number: 8918584Abstract: A method and apparatus for refreshing data in a flash memory device is disclosed. A counter is maintained for each memory block. When a memory block is erased, the counter for that erase block is set to a predetermined value while the remaining counters for other erase blocks are changed. When a memory block counter reaches a predetermined threshold value, the associated memory block is refreshed.Type: GrantFiled: January 9, 2014Date of Patent: December 23, 2014Assignee: Micron Technology, Inc.Inventor: Shuba Swaminathan