Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: A system is provided for digitizing the setting of a potentiometer of the type used in an analog joystick for computer games. The analog output of the potentiometer is applied to one of two inputs of a voltage comparator. When a readout of the joystick position is desired, a "write" input is applied to a counter to permit it to commence counting at a predetermined frequency from an initial or zero count. The digital outputs of the counter are coupled to the inputs of a digital-to-analog converter, the output of which is coupled to the second input of the voltage comparator. When the count in the counter produces a voltage at the output of the digital-to-analog converter corresponding to the voltage setting of the potentiometer, the comparator provides an output signal. The time delay from the time the write pulse occurs until this signal is obtained is representative of the potentiometer setting.

Abstract: A method and apparatus for losslessly compressing binary data using a technique referred to as Double Run-Length Encoding (DRLE). DRLE has particular application to the compression of gray-scale data as it is being processed for printing by a laser printer or other continuous raster scan device. DRLE records repeating patterns of ones and zeros with little computational complexity. Compression ratios that may be an order of magnitude or more are obtained frequently on data that may not compress well using traditional Run-Length Encoding (RLE). DRLE uses a sequential history of order-pairs that denote variable-length patterns of zeros and ones, and then encodes these patterns as they repeat themselves.

Abstract: A Digital-to-Analog (D/A) converter with programmable transfer function includes a Main Converter and at least one Sub-Converter. Errors in the Main Converter are compensated for by programming the one or more Sub-Converters with compensation values determined during a Calibration Sequence. The Calibration Sequence measures the deviations of the transfer function of the Main Converter from the ideal at predetermined bit transitions of the digital input signal and generates representative separate digital signals for the one or more Sub-Converters. By combining these separate signals with the digital input signal, the net errors of the D/A Converter transfer function are reduced.

Abstract: An absolute encoder is provided with a movable member, which may be a disc, a photodetector and a processing circuit. The movable member has a plurality of tracks T arranged from higher to lower orders, each track having a bright and dark pattern. The photodetectors A1-A4 receive a light through the bright and dark patterns to output triangular detection signals A1-A4 associated with the track T. The processing circuit processes the detection signals A1-A4 to produce bit signals P1-P3 which indicate a position of the movable member. The processing circuit is provided with an input unit 1, a comparator unit 2 and a logic unit 3. The input unit 1 receives the detection signals A1-A4 for producing a plurality of triangular wave signals having the same period but different phases. The comparator unit 2 comparatively processes the triangular wave signals with each other to produce a plurality of rectangular wave signals having different phases.

Abstract: A general digital-to-analog (DAC) topology spectrally shapes the DAC conversion noise caused by analog circuit mismatches. In particular, highly practical first-order and second-order noise-shaping DACs are special cases of a general topology. The topology extends the practicality of using noise-shaping DACs in .DELTA..SIGMA. data converters. The first-order DAC is at least as hardware efficient as previously known DACs, but offers the advantage that it is amenable to a simple dithering technique capable of eliminating spurious tones. The second-order DAC is more hardware efficient than previously known DACs, and generally has a large spurious-free dynamic range without any dithering. Moreover, the present invention allows DACs with other types of noise-shaping characteristics (e.g., bandpass noise-shaping characteristics) to be designed based on general DAC topology.