Abstract: Disclosed herein are combustion systems, power plants, and flue gas treatment systems that incorporate sweep-based membrane separation units to remove carbon dioxide from combustion gases. In its most basic embodiment, the invention is a combustion system that includes three discrete units: a combustion unit, a carbon dioxide capture unit, and a sweep-based membrane separation unit. In a preferred embodiment, the invention is a power plant including a combustion unit, a power generation system, a carbon dioxide capture unit, and a sweep-based membrane separation unit. In yet another embodiment, the invention is a flue gas treatment system that incorporates three membrane separation units with a carbon dioxide liquefaction unit.

Abstract: A two-stage process is provided for purifying off-gases from a high-pressure melamine plant. In the first stage, the off-gases are contacted with a recirculated urea melt containing melamine precursors and NH3. In the second stage, the off-gases are contacted with a fresh urea melt.

Abstract: A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

Abstract: A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio, in a packet switched network such as the Internet. An encoder at the sending end derives p redundancy blocks from each group of a k payload blocks and concatenates the redundancy blocks, respectively, with payload blocks in the next group of k payload blocks. At the receiving end, a decoder may recover up to p missing packets in a group of k packets, provided with the p redundancy blocks carried by the next group of k packets. The invention thereby enables correction from the loss of multiple packets in a row, without significantly increasing the data rate or otherwise delaying transmission.

Abstract: A request frame number indicative of a minimum frame number of data frames which have not been received and data frame reception confirmation information indicative of whether or not receptions of data frames from a frame number next to a minimum frame number in the data frames which have not been received to the last predetermined frame number have been confirmed are included in a feedback frame. Thus, there can be obtained a data communication method which makes it possible to reduce an unnecessary re-transmission to a reception side data communication apparatus carried out even when data frames transmitted from a transmission side data communication apparatus to the reception side data communication apparatus have been correctly received by the reception side data communication apparatus, and to hence improve a throughput of transmission of a data frame from the transmission side data communication apparatus to the reception side data communication apparatus.

Abstract: In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm.

Abstract: A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested by (1) applying a predetermined data pattern to the function, (2) computing a linear block error detection code residue from any output from the function being tested, and (3) comparing the residue to a error code residue (signature) derived from the output of a copy of the same function with the same data pattern. In one embodiment, the code signature has been previously derived from an error-free copy of the function. Where the signature is supplied contemporaneously by another copy of the same function also being tested, the function copy is not presumed error free. In both cases, any mismatch between the on-chip code residue and the signature indicates error, erasure, or fault. By either recursive reprocessing or shortening the intervals between comparisons, the mismatch can be located within a nested time or sequence interval.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor using pre-traceback shift registers and traceback memory. The decoder performs n-state Trellis decoding in real time while simultaneously de-interleaving a multiplexed data stream. The architecture can be expanded to provide programmable length traceback in a fixed number of clock cycles. The invention performs de-interleaving in parallel with the Trellis decoding, and symbols coming out of the decoder need no further processing for de-interleaving. Moreover, the invention allows complete traceback in one symbol period at video rates without the need for very high speed clocks or multi-read port memories. Programmability allows for flexible tradeoff of output error rate and traceback memory space.

Abstract: A method and apparatus for fast decoding of a Reed-Solomon codeword which includes storing the codeword in memory, finding syndromes of the codeword, using the syndromes to determine the number of errors in the codeword, which in turn are used to find an error locator polynomial for the codeword, which is a polynomial whose roots can be used to find the locations of the errors. This error locator polynomial is then be used to find the positions of the errors in the codeword. The positions of the errors in the codeword can be used along with the syndromes to determine the values of the errors in the codeword.

Abstract: An encoded loss resilient message includes data items, first redundant data items, and second redundant data items. Each of the first redundant data items corresponds to one or more associated data items. Each of the second redundant data items corresponds to one or more associated first redundant data items. The number of data items is greater than the number of first redundant data items which is in turn greater than the number of second redundant data items, thereby providing a cascading series of redundant data items.

Abstract: A scannable dynamic logic element includes a clock input, a test enable input, a data output, a precharge circuit, a boolean pull-down circuit and a test scan pull-down circuit. The precharge circuit is coupled between a first supply terminal and the data output and has a precharge control input coupled to the clock input. The boolean pull-down circuit is coupled between the data output and the second supply terminal and has a logic data input, a first evaluation control input which is coupled to the clock input and a first enable input which is coupled to the test enable input. The test scan pull-down circuit is coupled between the data output and the second supply terminal and has a test data input, a second evaluation control input which is coupled to the clock input and a second enable input which is coupled to the test enable input.

Abstract: A method and device for calculating syndromes used in forward-error-correction codes. To calculate syndromes more quickly using a computer with memory access latency, the polynomial equation C(X) is divided by a generator polynomial G(X) to form a remainder polynomial R(X). The remainder polynomial R(X) is then used to speed the calculation of the syndromes. A method of dividing a Nth order dividend polynomial by a 2R order divisor polynomial is also described. In addition, to further speed the calculation of syndromes, the generating polynomial is split into a number of sub-polynomials G.sub.j (X) to yield a number of remainder sub-polynomials R.sub.j (X) used to calculate the syndromes. Calculation of syndromes using evaluation by Horner's rule and a generalization thereof is also described.

Abstract: One embodiment of the invention is a method for locating an electronic device capable of sending e-mail. The method includes identifying that an e-mail is being sent from the electronic device. Next, the sender address is compared to an owner address. If the sender address does not match the owner address, the e-mail is redirected. In some embodiments, the method is performed by a computer. In other embodiments, the method is performed by a modem.

Abstract: A method for processing encoded data using error control coding in accordance with the present invention includes: a) obtaining Q codewords and P codewords from a storage location, wherein the Q codewords and the P codewords are all obtained in a single pass through the storage location, b) calculating P partial syndromes for said P codewords, c) calculating Q partial syndromes for the Q codewords, and d) storing the Q partial syndromes and the P partial syndromes in a buffer that is separate from the main memory. In some embodiments, storing the Q partial syndromes and the P partial syndromes in the buffer includes storing the Q partial syndromes in a first buffer, and storing the P partial syndromes in a second buffer.

Abstract: A method of simultaneously executing one or more computer application programs in one or more host computer system or server system under the control of a second computer system, where the host computer system or server system generates either presentation information or generic computer messages, or both, based on the application programs, involves establishing selected parameters in the host computer presentation information or messages, or both, interpreting selected portions of the host computer system's presentation information or message information, or both, as input to a computer program resident in the second computer system, examining the host computer system presentation information or message information, or both, at the second computer system to detect the presence therein of one or more of the selected parameters utilizing information in a custom object database, and continuing operation of the second computer system during the examining for the selected parameters.

Abstract: A method and apparatus for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble of a data field comprising 135 data bits and 9 check bits. 9 check bits are generated based on 135 data bits. The 9 check bits are appended to the data bits and the cumulative data field is checked for errors. An error detection syndrome is generated that indicates whether an error has occurred and whether the error is correctable. Check bit generation and error detection syndrome generation is accomplished based on the ordering in an ECC code matrix.

Abstract: A method for handling different of types of data bit errors in a computer system. In one embodiment, the method comprises the step of storing a data line in a first storage location. The method also includes the step of retrieving the data line from the first storage location. Data bit errors in the data line are detected and the data line is marked as containing a data bit error and stored in a storage location if the data line is not to be used immediately by a requesting process; otherwise error handling is performed by halting the requesting process.

Abstract: An error correcting apparatus and method of a digital processing system. The error correcting apparatus of the digital processing system includes a demodulator for demodulating channel data to source data and generating an error flag when an error occurs during demodulation, a synchronous detector for receiving the error flag and demodulation data generated from the demodulator and detecting a synchronizing signal to distinguish data by a unit of code which can correct an error, a first decoder for decoding the demodulation data and the error flag by a unit of row by the synchronizing signal to correct an error and an erasure, and a second decoder for decoding the demodulation data and the error flag by a unit of column by the synchronizing signal to correct an error and an erasure.

Abstract: A method of LBIST testing of the entire chip logic whereby intermittent faults can be eliminated. LBIST control logic is programmed to apply linehold states to specified latches within the chip. Latches which feed logic that has intermittent faults can be held to a specified `0` or `1` state such that the intermittent faults causing intermittent signatures can be eliminated. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. The LBIST design contains logic for generating linehold controls that will apply a specified linehold state to selected latches during the scan operation portion of the LBIST test.