Abstract: The present invention provides a robust global timing resynchronization architecture, a multi-link communications system including the same, and a method for minimizing the effects of resynchronization signal skew, reference clock skew, and PLL static phase error variations on resynchronization of multi-link communications systems.

Abstract: A single stage phase lock loop (PLL) is provided. The phase lock loop receives a reference clock frequency and is configured to output a PLL output frequency. The PLL output frequency is generated based on the reference clock frequency and a comparison clock frequency that is outputted by a modulator. An output divider is then applied to the PLL output frequency to generate a system output frequency. The modulator is configured to output a comparison clock frequency that is either a modulated clock frequency or unmodulated clock frequency. The modulated clock frequency and unmodulated clock frequency are alternatively generated based on a schedule. The desired rate may be at a granularity finer than a granularity that can be achieved by dividing the reference clock frequency by an integer.

Abstract: A system communicates data and includes an encoder for encoding communications data with a forward error correction code. A data randomizer randomizes the communications data with a random bit sequence and a combining circuit combines the communications data with known symbols into frames. A modulator maps the communications data into minimum shift keying or Gaussian minimum shift keying (MSK or GMSK) symbols based on a specific mapping algorithm to form a communications signal having an MSK or GMSK waveform over which the communications data can be transmitted.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: Correlation with a spreading code is done for each of the signals received by a plurality of antennas forming an array antenna (10); then, beam forming (18) is performed using the result of the correlation, and a delay profile is generated (20, 22, 26) from the result of the beam forming, thereby achieving accurate path detection (26). DOA information obtained for the beam forming (18) can also be used as an initial value to be given to a beam former (33) in a received signal processor (14).

Abstract: A method and system thereof for determining feedback for iterative channel estimation based on the summation of soft output decisions or Bit Error Rate (BER) derived from the output of an equalizer. The channel impulse response initially obtained according to a training sequence is used to estimate the received signal, and output hard values. The BER of the training sequence is calculated and judged, and if the BER is too high, the channel is estimated again according to the feedback until the BER satisfies a predetermined value. If the BER is still unsatisfactory after a predetermined number of trials, the channel is assumed to be an authentic bad channel, thus terminating the feedback procedure. If the equalizer is capable of outputting soft output decision, the summation of soft outputs is used instead of BER to determine whether feedback is appropriate.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.

Abstract: There is disclosed a duplex communication system having multiple antennae at the forward link transmitter. One method of transmitting a stream of information symbols from the antennae is by beamforming. With beamforming the transmitter typically operates in closed loop and uses channel information from the receiver to change beams in the forward link. Another approach employs orthogonal coding. Orthogonal coding can be simpler to implement because it can operate in an open loop system that is without channel knowledge at the transmitter. Each has its advantages and disadvantages. What is here disclosed is a method which is an alternative to using only beamforming or orthogonal coding. The signals transmitted from at least two antennae are by beamforming or orthogonal coding; or by beamforming in combination with orthogonal coding in a proportion that is determined by a reference value which is related to the differences between the signals from the antennae.

Abstract: A data communications system for communicating a data signal formed of successive data elements, said system comprising a transmission node; a reception node; and a link providing a data connection from said transmission node to said reception node; in which: said transmission node comprises a clock signal transmitter for transmitting a synchronisation clocking signal to said reception node via said link, said synchronisation clocking signal having synchronising features occurring at a frequency lower than a data element rate; an assembler for assembling elements of said data signal into data frames, each data frame having a plurality of successive data elements of said data signal, for transmission to said reception node via said link, said assembler being responsive to said synchronisation clocking signal so as to set a synchronisation flag associated with a data element having a first predetermined temporal relationship with a synchronising feature of said synchronisation clocking signal; and said receptio

Abstract: Embodiments of system and method for determining channel coefficients in a wireless network are generally described herein. Other embodiments may be described and claimed. In some embodiments, channel coefficients of a multiple-input multiple-output (MIMO) channel may be determined without interpolation.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.

Abstract: A feedforward filter has a plurality of feedforward filter taps, including a feedforward filter reference tap. The reference tap of the feedforward filter is positioned proximate a center position of the feedforward filter. A ramping circuit assembly has an input port configured to receive at least one decision feedback filter tap coefficient from a decision feedback filter. A coefficient ramping circuit is configured to provide a ramped output for at least one of the decision feedback filter tap coefficients. The ramped output is varied over time from a first value to a second value. The second value is dependent upon the value of a decision feedback filter tap coefficient. An output port of the ramping circuit assembly is configured to communicate information representative of the ramped output(s) to a precoder.

Abstract: This invention extends Alamouti's scheme for wideband TDMA systems; it then works in conjunction with time-domain equalization. In fact, the present invention envisages time-domain DFE or MLSE equalization (which is more robust than linear frequency-domain equalization) via the use of a training mid-amble to separate adjacent sub-blocks; this mid-amble is used in equalizer training and its direct and inter-symbol interference contributions to the received signal, are subtractively eliminated to facilitate the detection process itself. This approach may be applied to all systems in time-dispersive propagation media, where the burst or slot length is short enough that the fading can be considered time-invariant over its duration.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.

Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.

Abstract: There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, having a signal converting section for calculating a spectrum of the signal-under-measurement, a bandwidth calculating section for calculating frequency where a saturation rate of a value of the integrated spectrum of the signal-under-measurement becomes almost equal to a saturation rate set in advance in a band-to-be-measured set in advance as upper cutoff frequency of the band-to-be-measured to calculate the jitter and a jitter calculating section for measuring the jitter in the signal-under-measurement based on the spectaum in the band-to-be-measured of the signal-under-measurement.