Abstract: A computer-implemented method, according to one approach, includes: receiving an indication that memory has entered a protected state. Additionally, I/O requests intended for target locations in the memory are received. A determination is made as to whether the target locations are permitted to perform I/O requests while the memory is in the protected state. In response to determining one or more of the target locations are not permitted to perform I/O requests while the memory is in the protected state, the respective one or more of the received I/O requests are denied. However, in response to determining one or more of the target locations are permitted to perform I/O requests while the memory is in the protected state, the respective one or more of the received I/O requests are performed at the one or more target locations.

Abstract: The present disclosure provides methods, systems, devices, and media for data processing. The method may include obtaining information of one or more hard disks of each of one or more data nodes, the information of the one or more hard disks at least including type information, capacity information, and location information of each of the one or more hard disks; determining, based on a data processing instruction and the information of the one or more hard disks, target information of a target hard disk among the one or more hard disks; and transmitting the data processing instruction including the target information of the target hard disk to a target data node corresponding to the target hard disk.

Abstract: Near-cache compute can be implemented by a device that includes an interface configured to communicate with external entities and processing circuitry configured to receive a recall count request, from an entity on the interface. Here, the recall count request can specify a data object that is represented by a set of cache lines on the device. The device can tabulate a number of cache lines in the set of cache lines that are inconsistent to create a recall count and communicate a response to the entity via the interface that includes the recall count.

Abstract: The present application discloses a memory device, a control method of a memory device, and a memory system, and belongs to the technical field of memory device. The control method includes: a peripheral circuit receiving an erase instruction, and recording a number of the received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in a memory cell array; and the peripheral circuit, in response to the number of the received erase instructions reaching a number threshold, selecting one memory page in a first memory block of the memory cell array to perform program processing.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.

Abstract: According to one embodiment, a memory controller includes a parameter table having entries which respectively correspond to superblock address ranges. The memory controller translates a logical address of data to be written to the memory into a superblock address, calculates compression parameters which correspond to items of data to be written to superblock addresses, writes the compression parameters to the parameter table, and compress data using the parameter table.