Patents Examined by Jason W Blust
  • Patent number: 11188265
    Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: November 30, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Sheng-I Hsu, Ching-Chin Chang
  • Patent number: 11182158
    Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Bruce Querbach, Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram
  • Patent number: 11182084
    Abstract: Various embodiments manage dynamic memory allocation data. In one embodiment, a set of memory allocation metadata is extracted from a memory heap space. Process dependent information and process independent information is identified from the set of memory allocation metadata based on the set of memory allocation metadata being extracted. The process dependent information and the process independent information at least identify a set of virtual memory addresses available in the memory heap space and a set of virtual memory addresses allocated to a process associated with the memory heap space. A set of allocation data associated with the memory heap space is stored in a persistent storage based on the process dependent information and the process independent information having been identified. The set of allocation data includes the process independent allocation information and a starting address associated with the memory heap space.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michel Hack, Xiaoqiao Meng, Jian Tan, Yandong Wang, Li Zhang
  • Patent number: 11169931
    Abstract: Techniques for obtaining metadata may include: receiving, by a director, an I/O operation directed to a target offset of a logical device, wherein the director is located on a board including a local page table used by components on the board; querying the local page table for a global memory address of first metadata for the target offset of the logical device; and responsive to the local page table not having the global memory address of the first metadata for the target offset of the logical device, using at least a first indirection layer to obtain the global memory address of the first metadata. The global memory may be a distributed global memory including memory segments from multiple different boards each including its own local page table. Compare and swap operations may be used to perform atomic operations to ensure synchronized access when updating the distributed global memory.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: November 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Kevin Tobin
  • Patent number: 11157411
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
  • Patent number: 11132213
    Abstract: Systems and methods are described for transforming a data set within a data source into a series of task calls to an on-demand code execution environment. The environment can utilize pre-initialized virtual machine instances to enable execution of user-specified code in a rapid manner, without delays typically caused by initialization of the virtual machine instances, and are often used to process data in near-real time, as it is created. However, limitations in computing resources may inhibit a user from utilizing an on-demand code execution environment to simultaneously process a large, existing data set. The present application provides a task generation system that can iteratively retrieve data items from an existing data set and generate corresponding task calls to the on-demand computing environment. The calls can be ordered to address dependencies of the data items, such as when a first data item depends on prior processing of a second data item.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 28, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Marc John Brooker, Ajay Nair
  • Patent number: 11127468
    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Marc Battista
  • Patent number: 11119688
    Abstract: The present disclosure provides a replica processing method based on a raft protocol. The method includes: for a node to be processed corresponding to a raft replica group, determining a replica to be cleaned corresponding to the node, the raft replica group including a first node and at least one second node; for the node, obtaining replica configuration information of the raft replica group, the replica configuration information including one or more primary replicas stored by the first node and one or more secondary replicas stored by the at least one second node; and for the node, determining whether the replica configuration information includes the replica to be cleaned, if yes, reserving the replica to be cleaned, and if no, deleting the replica to be cleaned. The present disclosure also provides a replica processing node, a distributed storage system, a server, and a computer-readable medium.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 14, 2021
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Zhengli Yi, Pengfei Zheng, Xinxing Wang
  • Patent number: 11119932
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bradly G. Frey, George W. Rohrbaugh, III, Brian W. Thompto
  • Patent number: 11119934
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory controller having a map manager and preload mapping information storage, and a memory device having logical-to-physical mapping information. The memory controller determines and obtains from the memory device, preloads mapping information, and then stores the preload mapping information in the preload mapping information storage, before a map update operation of the logical-to-physical mapping information is performed. The preload mapping information includes logical-to-physical mapping information to be updated.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Byeong Gyu Park, Sung Hun Jeon, Young Ick Cho, Seung Gu Ji
  • Patent number: 11119656
    Abstract: Systems and methods of deduplication aware scalable content placement am described. A method may include receiving data to be stored on one or more nodes of a storage array and calculating a plurality of hashes corresponding to the data. The method further includes determining a first subset of the plurality of hashes, determining a second subset of the plurality of hashes of the first subset, and generating a node candidate placement list. The method may further include sending the first subset to one or more nodes represented on the node candidate placement list and receiving, from the nodes represented on the node candidate placement list, characteristics corresponding to the nodes represented on the candidate placement list. The method may further include identifying one of the one or more nodes represented on the candidate placement list m view of the characteristic and sending the data to the identified node.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 14, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Robert Lee, Christopher Lumb, Ethan L. Miller, Igor Ostrovsky
  • Patent number: 11112971
    Abstract: A storage device includes one or more FMPKs including a FM chip capable of storing data and a storage controller that controls storing of write data of a predetermined write request for the FMPK. The FMPK includes a compression/decompression circuit that compresses data according to a second compression algorithm different from a first compression algorithm. The storage controller compresses data using the first compression algorithm, and determines whether the write data will be compressed using the storage controller or the compression/decompression circuit based on a predetermined condition. The write data is compressed by the determined storage controller or compression/decompression circuit and is stored in the FMPK.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 7, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ai Satoyama, Tomohiro Kawaguchi, Yoshihiro Yoshii
  • Patent number: 11112998
    Abstract: The present invention discloses an operation instruction scheduling method and device for a NAND flash memory device. The method comprises: performing task decomposition on the operation instruction of the NAND flash memory device, and sending an obtained task to a corresponding task queue; sending a current task to a corresponding arbitration queue according to a task type of the current task in the task queue; and scheduling a NAND interface for a to-be-executed task in the arbitration queue according to priority information of the arbitration queue. Embodiments of the present invention can efficiently realize operation instruction scheduling of a NAND flash memory device, improve flexibility of operation instruction scheduling of the NAND flash memory device, and improve overall performance of the NAND flash memory device.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 7, 2021
    Assignee: DERA CO., LTD.
    Inventors: Wang Fenghai, Xia Jiexu, Wang Song, Yang Ji, Zhang Jiantao
  • Patent number: 11099748
    Abstract: A radiation hardened, digital to analog converter includes first and second serial communication circuits, a common bus interface configured to connect the first and second serial communication circuits to first and second digital serial communication buses, respectively, and a digital to analog converter circuit, where the first and second serial communication circuits are configured to receive data over the first and second digital serial communication buses, respectively, for use by the digital to analog converter circuit.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 24, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: James E. Fraction, Andrzej T. Jackowski
  • Patent number: 11093161
    Abstract: An apparatus includes a processing device comprising a processor and a memory. The processing device is configured, in conjunction with synchronous replication of a logical storage volume between first and second storage systems, to receive a synchronous write request comprising at least a portion of a data page to be written to the storage volume, to determine a source processing module associated with the data page in the first storage system, to determine at least one of a process identifier and a processor identifier of the source processing module in the first storage system, and to select a particular one of multiple links between the first and second storage systems for use with the synchronous write request based at least in part on at least one of the process identifier and the processor identifier of the source processing module. The selected link is illustratively associated with a transmit processing module.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, David Meiri
  • Patent number: 11055024
    Abstract: In a computer which controls data access with respect to a prescribed logical unit, a processor is configured to: perform, when data access by one path with respect to a logical unit is not completed, control for switching paths with respect to the logical unit; perform communication control in accordance with SCSI with the logical unit by executing a SCSI driver; accept a path interchange time that is a time used as a reference for switching paths with respect to the logical unit; determine an upper limit number of retries in data access by the one path on the basis of the path interchange time; and perform control so that an upper limit number of retries using the one path by the SCSI driver equals the determined number of retries.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Hitachi, Ltd.
    Inventor: Yuuki Kuroda
  • Patent number: 11048414
    Abstract: A method and apparatus for managing data access comprises: receiving a write request for writing data into one or more storage blocks; in response to determining that a storage block is unavailable, writing a part of the data into a virtual storage block corresponding to the storage block, the part of the data being required to be written into the storage block; and in response to determining that the storage block becomes available, copying the part of the data from the virtual storage block to the storage block. The embodiments of the present disclosure further disclose a corresponding apparatus. By introducing the virtual storage blocks in the data access, the embodiments of the present disclosure can realize the parallel data transfers of a plurality of writes and thus greatly improve the data writing performance of the system.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Ruiyong Jia, Jian Gao, Lifeng Yang, Xinlei Xu, Jibing Dong
  • Patent number: 11016685
    Abstract: A method and a defragmentation module for defragmenting resources of a hardware system. The defragmentation module identifies a set of structures. Each structure of the set of structures partially hosts a respective set of host machines. Respective resources of each host machine of the respective set of host machines are allocated in at least two structures of the set of structures. The defragmentation module selects, from the respective resources of a host machine of the respective set of host machine, a remote resource of a first structure being different from a second structure partially hosting the host machine. A remote amount of the remote resource is less than an amount of available resources of the second structure. The defragmentation module assigns the remote amount of the available resources of the second structure to the host machine instead of the remote resource.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 25, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Vinay Yadhav, Daniel Turull
  • Patent number: 11016887
    Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Wan-Jun Roh
  • Patent number: 11003602
    Abstract: The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker