Abstract: In a digital/analog converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)-th capacitor has a unit capacitance, and a 2k-th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)-th capacitor is connected to a first terminal of the 2k-th capacitor. Also, if m is 1, 2, . . . , n−1, an m-th coupling capacitor is connected between the first terminal of the 2m-th capacitor and the first terminal of the (2m+t)-th capacitor, while an (n−1)-th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′-th one of coupling capacitor has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)-th coupling capacitors.

Abstract: A stream of channel bits, of a signal relating to a binary channel, is decoded into a stream of source bits, of a signal relating to a binary source. This binary channel includes a main channel and a secondary channel. This secondary channel is embedded in the main channel. Errors in the stream of secondary channel bits are corrected using a stream of corrected main channel bits. This stream of corrected main channel bits is reconstructed from a stream of corrected source bits. The secondary channel can be embedded in the main channel in different manners, e.g. via multi-level coding or via merging-bit coding.