Patents Examined by Jeff Natalin
  • Patent number: 9116164
    Abstract: A pseudo-differential accelerometer resistant to EMI is disclosed that includes a device with a sensor core connected to an integrated circuit including a chopper, differential amplifier, and dummy core. The chopper swaps input to output connections during different states. The dummy core is coupled to a dummy chopper input. Three bond wires coupling the sensor output to a sensor chopper input, a first chopper output to a first sensor input, and a second chopper output to a second sensor input can connect the sensor and integrated circuit. The device can include a dummy pad and dummy bond wire connecting the dummy pad to the dummy chopper input. This configuration requires four bond wires connecting the sensor and integrated circuit. A neutralization core can be connected to the sensor chopper input. The chopper can change states to smear noise across a wide range, or away from a band of interest.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 25, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ganesh Balachandran, Vladimir Petkov
  • Patent number: 8164344
    Abstract: An electric vehicle incorporates a ground fault detecting system for preventing a ground fault detector from detecting a ground fault in error. First and second ground fault detectors are associated respectively with first and second ungrounded power supplies which generate respective different voltages. Since the first and second ground fault detectors are activated in different periods, the ground fault detecting system prevents a ground fault from being detected in error.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 24, 2012
    Assignee: Honda Motor Co., Ltd.
    Inventors: Mitsuteru Yano, Toshiaki Takeshita
  • Patent number: 8058883
    Abstract: Disclosed herein is a method for detecting capacitance including: allowing an oscillator to output a plurality of time division oscillation frequencies according to the capacitance detected by a capacitance detection plate; counting the plurality of time division oscillation frequencies during a predetermined time period; and offsetting increasing and decreasing of the oscillation frequencies due to noise such that a count value becomes uniform over the predetermined time period. Even when external noise is applied, distortion of the oscillation frequency due to the external noise is minimized and the oscillation frequency varies depending on only the capacitance of the capacitance detection plate. Accordingly, it is possible to prevent an error due to the noise at the time of the detection of the capacitance.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: November 15, 2011
    Assignee: AD Semiconductor Co., Ltd.
    Inventor: Sang-Chuel Lee
  • Patent number: 8013592
    Abstract: The technology relates to detecting the wiring phase of an unknown phase voltage relative to a reference phase voltage in an electric power distribution system having a polyphase power line. In order to reliably detect the wiring phase at the remote location relative to a reference wiring phase even if the remote location is at a larger distance from the reference location, at least one relay location is arranged between the reference location and the remote location and connected to the wiring phase of the polyphase power line. A first phase relation is detected between the reference wiring phase voltage at the reference location and the wiring phase voltage at the relay location. A second phase relation is detected between the wiring phase voltage at the relay location and the wiring phase voltage at the remote location. The wiring phase of the remote location relative to the wiring phase at the reference location is detected based on the first phase relation and the second phase relation.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: September 6, 2011
    Assignee: Enel Distribuzione S.p.A.
    Inventors: Paolo Giubbini, Fabio Veroni
  • Patent number: 7095289
    Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: August 22, 2006
    Assignee: Intel Corporation
    Inventors: Ernest Knoll, Eyal Fayneh