Patents Examined by Jeff Zweizig
  • Patent number: 6084445
    Abstract: An initialization strap is disclosed. The initialization strap includes an electronic device capable of receiving a control signal and of transmitting a first output signal in response thereto; a first diode capable of receiving the first output signal, the first diode being forward biased when the first output signal is received and being reverse biased otherwise; a first line over which the electronic device may transmit the first output signal to the first diode; and a first resistor capable of tying the line to a first predetermined voltage level.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: July 4, 2000
    Assignee: Intel Corporation
    Inventor: Chengwu Chen
  • Patent number: 6057721
    Abstract: A fast start-up circuit for use in integrated circuits where there are internal nodes of reference circuits that need to be charged to a predetermined voltage level at a quicker rate than that delivered by the typical ramping up of supply power. The circuit a current driven approach, which is unique from the voltage driven approaches found in the prior art. The circuit is comprised of a high gain reference circuit and a current generator. The reference circuit is comprised of a bias generator and a high gain amplifier. The invention is characterized by a current generator which is capable of rapidly injecting relatively high levels of current into the reference circuit or sinking relatively high levels of current from the reference circuit or both. The invention is further characterized by a current driven feedback loop which deactivates the current generator once start-up is achieved and the high gain reference circuit approaches the quiescent point.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: May 2, 2000
    Assignee: Microchip Technology Incorporated
    Inventors: James B. Nolan, David Susak
  • Patent number: 6020778
    Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: February 1, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto