Abstract: The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the stages being coupled together by a data path, at least one stage being coupled to a transceiver which causes data to be provided to the stage for processing or to bypass the stage unprocessed in response to a stage enable signal; a synchronizer which receives processed data from the stages and causes the processed data to be provided to external logic in synchronization with a clock signal.

Abstract: An input video signal is reduced according to size reduction ratio data K in an input processing section and written into alternate field memories. The written reduced video signal is alternately read from the field memories in a display processing section and processed for window displaying. Video reduction control sections are provided on the respective input and display sides, so that various signals, such as RHOLD, ADCANS, RACK signals, etc., are exchanged therebetween. When a size reduction ratio data K is changed, on the display side a read memory is fixed on a first field memory and size data is fixed, while on the write side video data is written into a second field memory, based on the new reduction ratio. After updating the size data on the display side, video data is read from the second field memory at the new reduction ratio.

Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Abstract: A dedicated context cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits, and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents an ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. A multiplexer circuit is also provided for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit.

Abstract: A document display system arranges images of a document ordered in a linear array of pages on a display screen. One page of the document is defined as a focus page which is displayed at the center of the display screen. Images of pages preceding the focus page in the linear array of pages are presented to a user using a first recursive block that is located to the left of the focus page on the display screen. Images of pages following the focus page in the linear array of pages are presented to a user using a second recursive block that is located to the right of the focus page on the display screen. Each recursive block is initially filled with images that are arranged proximate to the focus page in the array of pages. This arrangement of the pages of a document on the display screen provides a context within which to view the selected focus page of a document.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Abstract: A method and apparatus for storage and retrieval of multiple data streams in a multimedia distribution system. A given data stream is separated into a plurality of portions, and the portions are stored in a multi-disk storage system with Y disks each having X zones such that the ith portion of the given stream is stored in zone (i mod X) of disk (i mod Y). The number X of zones per disk and the number Y of disks are selected as relatively prime numbers. The stored data are retrieved using Y independent retrieval schedulers which are circulated among the Y disks over a number of scheduling intervals. Each retrieval scheduler processes multiple requests separated into X groups, with the requests of each group accessing the same disk zone during a given scheduling interval. The retrieval schedulers are also configured such that the retrieval requests of a given retrieval scheduler access the same disk during a given scheduling interval.

Abstract: Embodiments of the present invention are capable of hiding a message, such as, for example, a copyright notice or other indicium of authorship, in an electronic document. An illustrative embodiment of the present invention comprises encoding an electronic document with a plurality of tags from a case insensitive markup language; and modulating the case of at least one tag character in at least one of said plurality of tags with a binary string, wherein the binary string represents a message to be hidden in the electronic document.

Abstract: A a client web browser receives a first user selection of a link displayed on a web page. The first user selection indicates a preference by the user for deferred display of another web page corresponding to the link. In response to the first user selection, the web browser loads the other web page from a server or other remote repository into a memory device local to the client web browser. Next, the user makes a second selection of the link (after the first user selection). The second user selection indicates a preference by the user for immediate display of this other web page. In response, the web browser fetches and displays this other web page from the local memory.

Abstract: A large collection of data is represented as a hierarchy of two-dimensional maps displayed on a computer monitor. The collection of data is used to generate an incidence matrix, representing interrelationships among elements of the data. The incidence matrix is then used to construct a hierarchy of planar graphs. Each graph is converted into a two-dimensional map which shows conventional geographical features, these geographical features being used to represent symbolically various aspects of the data. The user of the system sees a large-scale map, preferably having the form of a globe, which represents the entire data collection. By expanding more detailed portions of the large-scale map, the user gains access to a plurality of lower-level maps which represent more detailed information about the collection of data.

Abstract: An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

Abstract: A text string extraction system for a computer system having a display, an operating system having an application program interface with text output portion, a cursor for moving on the display, and application programs to be executed on the operating system for outputting text strings onto operating system via the text output portion to display the text strings on the display, the extraction system includes drawing portion for drawing a symbol on a location pointed to by the cursor and having the operating system output a signal to the application program and having the application program output a text string to be re-displayed and input portion for extracting a text string beside the location pointed to by the cursor by receiving the text string to be re-displayed output from the application program thereby supplying the input text string to the operating system via the text output portion for re-displaying.

Abstract: A system and method for providing speed-regulated data transmission between two synchronous systems in different clock domains. A first synchronous circuit includes a memory device, and a second synchronous circuit includes one or more data-requesting devices. The first synchronous circuit operates at a greater clock speed than the clock speed of the second synchronous circuit. A read request buffer queues read request signals from the data-requesting devices, and outputs one of the read request signals to the memory device. A pulse generator receives the read request signal which was output from the queue, and generates a plurality of signal pulses in response thereto. Each of the pulses occurs at a different predetermined time from the occurrence of the read request signal. One of the pulses is selected to be the read acknowledge signal, and assertion of the read acknowledge signal allows the read request buffer queue to output another read request signal.

Abstract: A qualified burst cache facilitates burst mode data transfer between a first clock domain and a second clock domain by simplifying cache control structures. A cache is marked as qualified when full or there is no more data to be written to the cache, allowing burst data to be transferred out of said cache. The invention has applications in network adapter cards for transferring data between a host system bus and a network where the bus and network operate at different speeds and are therefore part of different clock domains.

Abstract: A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and two ROP bits. The ROP bits indicate a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified.

Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.

Abstract: A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

Abstract: Blocks of data are transferred in burst mode from a first device attached to a first bus, to a second device attached to a second bus having time multiplexed address/data lines. A bridge circuit includes an address register, which is coupled to the first bus, a circuit for incrementing the address register, and an output register coupled to the address/data lines of the second bus. In an aborted burst mode transfer of a block of data from one device to the other in which a "last" data byte in the block was successfully transferred, but a "next" byte of data was not successfully transferred, the system provides for an efficient retry of the transfer of the aborted data block. This efficient retry is accomplished in part by swapping the information in the address register of the bridge circuit with the information in its output register, such that the output register contains the address of the "next" data byte.

Abstract: A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters is configured to generate a grading signal following a particular bus transaction to indicate whether the latency in obtaining the bus during the previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or reached a critical or near-critical point).