Abstract: A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

Abstract: Systems and methods for performing low-density parity-check (LDPC) coding may include a wireless communication device that determines a count of a plurality of information bits. The wireless communication device may select a codeword length according to the count. A LDPC encoder of the wireless communication device may generate a codeword for the plurality of information bits, the codeword having the codeword length. The wireless communication device may transmit the codeword to an LDPC decoder of another wireless communication device.

Abstract: An error rate measurement apparatus includes a display control unit, an operation display unit, and a control unit. The display control unit displays a firsts coefficient value in a selectable manner by tabs of a number corresponding to a Full Swing value, performs matrix display on a display screen by using each one of combinations of each second coefficient value and each third coefficient value in the first coefficient value on the selected tab, and displays each coefficient value on the display screen in a three-dimensional bird-eye view by using each second coefficient value and each third coefficient value as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis and using the first coefficient value as a depth direction coordinate axis. The operation display unit selects a range including at least one cell as a scanning target in the matrix display or a bird-eye display.

Abstract: Disclosed is an operating method of a memory, and the operating method may include reading, from selected memory cells included in the memory, codewords including data and an error correction code; detecting errors in the codewords; correcting the errors in the codewords; re-writing the error-corrected codewords to the selected memory cells; re-reading the re-written error-corrected codewords from the selected memory cells; and determining whether the errors are permanent errors in response to a determination that an error is present in the re-read error-corrected codewords.

Abstract: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction.

Abstract: A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: Systems, computer-implemented methods or computer program products to facilitate mitigating quantum errors associated with one or more quantum gates. A noise modeling component can generate a sparse error model of noise associated with one or more quantum gates; employ the sparse error model; and draw samples from an inverse noise model. An insertion component can insert the samples to mitigate errors associated with the one or more quantum gates. The insertion component can reduce the noise by running circuit instances augmented with samples from the inverse noise model. The noise modeling component includes a noise shaping component that can shape the noise affecting one or more quantum gates by twirling to form a Pauli channel.