Abstract: A method is provided for fabricating a stacked capacitor in a storage node (memory cell) of a dynamic random access memory (DRAM) that exceeds the photolithography limit. A DRAM has an array of memory cells and each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, drain and gate. The drain is coupled to a bit line, and the gate coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of each of the memory cell transistors. A protective layer is patterned and formed over a predetermined portion of the lower conductive layer for defining an inter-capacitor isolation region. A portion of the lower conductive layer is removed to form a bottom plate of the capacitor associated with each memory cell, such that a protected portion of the lower conductive layer under the protective layer is removed.