Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.

Abstract: Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a donor substrate bank that is capable of supporting a plurality of donor substrates on which a plurality of micro LEDs are formed. In an embodiment, the donor substrate bank is moveable in the X, Y, and Z directions. In an embodiment, the system may also include a host substrate table that is capable of supporting a host substrate. The host substrate may include a plurality of segments. In an embodiment, the host substrate table is moveable in the X, Y, and Z directions. Embodiments of the invention may also include an array of macro transfer heads. In an embodiment, each macro transfer head may include a plurality of micro transfer heads.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

Abstract: A simultaneous ohmic contact to silicon carbide includes a mixture of platinum, titanium, and silicon compounds deposited on a silicon carbide substrate. The silicon carbide substrate includes an n-type surface and a p-type surface.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

Abstract: A method for enhancing charge carrier mobility of a field-effect transistor device. The method comprises generating uniaxial nanogrooves on a substrate and blade coating a solution comprising a semiconducting polymer onto the substrate. The polymer solution is spread onto the substrate in a direction parallel to the nanogrooves and a main-chain axis of the polymer is parallel to the nanogrooves. The semiconducting polymer can be then annealed, so that a polymer film is formed which is layered on top of the substrate, with polymer chains aligned parallel to a direction of charge carrier movement.

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with multi-trench enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having an opposite, second conductivity type. The device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region and extends from the first control trench to the first second depletion trench and further from the first depletion trench to the second depletion trench.

Abstract: A semiconductor device includes a semiconductor substrate having a fin structure. A gate structure is disposed over the fin structure. A first dielectric layer is disposed on the gate structure and the fin structure. A contact plug is disposed in the first dielectric layer and electrically connected to source/drain region in the fin structure. A second dielectric layer is disposed on the first dielectric layer. the second dielectric layer has a first nitride layer and a first etch stop layer, and the first nitride layer is disposed on the first etch stop layer. A via goes through the second dielectric layer and electrically connected to the contact plug. A metal layer is disposed on the second dielectric layer.

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Abstract: An LED chip for use in an LED chip array forming a continuous array of LEDs. The LED chip comprises an array of LEDs on a substrate. LEDs in a row of the array are longitudinally offset from corresponding LEDs in another row. Adjacent LEDs in each row of the array are separated by a longitudinal pitch. At least part of an end face of the substrate is angled with respect to a transverse axis of the LED chip such that the LED chip is positionable adjacent another LED chip to maintain the longitudinal pitch between adjacent LEDs on different chips.

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Abstract: A method may include depositing a first conductive material in an opening disposed between a first semiconductor structure and a second semiconductor structure, the first conductive material comprising at least one first void. The method further includes removing a portion of the first conductive material to form a trench, the trench exposing the at least one first void and being defined by a remaining portion of the first conductive material; and depositing a second conductive material in the trench, the second conductive material and the remaining portion of the first conductive material forming a dummy gate layer.