Abstract: A read-only memory (ROM) and method for manufacturing a ROM having trench-type gate regions and source/drain regions, wherein the trench-type gate regions are provided in a substrate. The ROM further includes an insulating layer for isolating the substrate from the source/drain regions so to prevent current leakage between the source/drain regions and the substrate and to reduce area required by components of the ROM, thereby increasing component integration. The ROM also comprises a checkerboard conductive layer having a plurality of parallel source/drain regions a plurality of parallel channel regions connected to the plurality of parallel source/drain regions, wherein the plurality of parallel source/drain regions and the plurality of parallel channel regions cross each other at right angle, while the source/drain regions and the trench-type gate regions are approximately parallel to each other.