Patents Examined by Jerry Smith
  • Patent number: 5450339
    Abstract: A noncanonic fully systolic least mean squares adaptive filter architecture encompasses both tap weight updates and filtering and allows cascadability without penalties in speed or accuracy. A systolic tap weight update section is followed by a systolic FIR filter section. An array control and alignment section and a forward loading shift register provides a modified coefficient update circuit which facilitates the interface between the two sections. This architecture allows for efficient microprocessor control of the filter algorithm.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: September 12, 1995
    Inventors: David B. Chester, William R. Young
  • Patent number: 5440495
    Abstract: A control device for weft inserting in a jet loom realizes weft inserting in stable running conditions without depending on the professional perceptions and experiences of operators. The control device for weft inserting is constructed by inferring a corrected value of at least one parameter for weft inserting by fuzzy inference on the basis of at least one operating information relating to the weft inserting in a weaving machine in order to accept an operating condition of the weaving machine at an objective value, and controlling at least one actuator for weft inserting on the basis of the corrected value inferred by the fuzzy inference.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: August 8, 1995
    Assignee: Tsudakoma Kogyo Kabushiki Kaisha
    Inventors: Tsutomu Sainen, Shigeo Yamada
  • Patent number: 5412577
    Abstract: A control system is disclosed for controlling misregistration between the colors of an image printed on a web. The system includes an imaging device such as a camera or group of cameras, a processor, and image conversion circuits coupled to the processor. The system detects print color misregistration based upon the signals produced by the imaging device as a result of scanning the printed image. The conversation circuits convert the signals to signals usable by the processor to determine the color densities of the various colors within the image. These color densities are compared with reference color densities stored in a memory of the processor, where the reference color densities may be generated from a source such as the printing plates used to print the image for which misregistration is being monitored.
    Type: Grant
    Filed: October 28, 1992
    Date of Patent: May 2, 1995
    Assignee: Quad/Tech International
    Inventors: Jeffrey W. Sainio, John C. Seymour
  • Patent number: 5379229
    Abstract: An automated system for storing and retrieving objects from multiple object categories. A plurality of storage rack assemblies is included. Each storage rack assembly has a plurality of slots sized for storing objects. A storage transport is movable alongside each respective storage rack assembly for positioning adjacent any slot. A plurality of horizontal tracks are arranged to be perpendicular to the storage rack assemblies. Each storage rack assembly has an end adjacent the tracks. A runner transport is coupled to and movable on each track for receiving one of the objects from, or providing one of the objects to a storage transport. Two conveyor rack assemblies are located at opposite ends of the tracks, aligned perpendicularly to the track. Conveyor transports are adjacent the conveyor rack assemblies for transferring objects between the conveyor rack assembly and the runner transports.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: January 3, 1995
    Assignee: Communications Test Design, Inc.
    Inventors: Donald F. Parsons, Kyle Gress, James M. Dempsey, Joseph Ross, William Parsons, Stephen Parsons
  • Patent number: 5377116
    Abstract: A method of designing a cutting tool uses finite element numerical models to predict a response of the tool during a simulated cutting operation on a workpiece, and to simulate a chip-flow phenomenon occurring during the cutting operation. The chip-flow model incorporates representations of a fracture mechanism describing a chip separation phenomenon, a heat-generating mechanism describing a thermal coupling phenomenon, and a shear localization mechanism describing a shearing phenomenon wherein these phenomena occur during the cutting operation. The predicted tool response and the chip-flow simulation are evaluated by an artificial intelligence system to render rule-based judgments which are embodied in recommendations for continuously modifying the models and input design variables until the simulation and response converge to an optimal result.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: December 27, 1994
    Assignee: Valenite Inc.
    Inventors: Steven F. Wayne, David A. O'Neil, Charles E. Zimmerman, Yefim Val
  • Patent number: 5377120
    Abstract: An apparatus ideally suited for the small mailing service is disclosed. The apparatus can take pro-printed, un-addressed mail pieces of non-identical size delivered to the mailing service from different merchants and combine the mail pieces to create mailing bundles at the lowest postal rate and group the bundles to create a single mailing. In the apparatus a computer serves to take the merchant mailing lists, merge and sort the entries thereon into lowest postal rate groupings, and use this merged data base to enable a sequence controller and associated machinery to physically commingle and address the non-identical mail pieces into the single mailing bundle. Provision is also made for generating required postal service documentation and invoices from the mailing service to the merchants.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: December 27, 1994
    Inventors: Carl L. Humes, Lawrence W. Dougherty
  • Patent number: 5373438
    Abstract: In the sequence program (ladder circuit), in order to give a common address between contacts of the ladder circuit longitudinally and store states before and after the processing of the contact in the ladder circuit, two types of memories corresponding to addresses at the both ends of the contact are provided and a compiler for classifying the processing into the five types and a sequence execution unit for processing a machine language of the compiler are further provided so that execution can be made even if an output instruction is provided in an intermediate portion of the ladder circuit.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: December 13, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroto Miyazaki, Toshihiro Ide, Akiho Hirahata
  • Patent number: 5369566
    Abstract: A method of programming a programmable controller in a manner by which a variety of menus, options, or questions seeking limited parameter answers are presented to the user; for example, setup parameters such as the type of labware, source and destination of reagent transfer etc. for conducting a particular biological and chemical assay experiments by an automated laboratory workstation. Software "templates" are used to focus the request for parameters from the user to tailor user needs to the laboratory workstation's capabilities. The software templates are designed to accommodate a wide variety of experimental setups in accordance with the setup parameters input by the user. By providing the parameters with the assistance of the templates, the user may program a complete set of instructions for conducting a biological or chemical assay. The instructions may include the time and method for undertaking the experiment.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: November 29, 1994
    Assignee: Beckman Instruments, Inc.
    Inventors: Dale R. Pfost, Robert M. Coppock, Donald S. Murray, R. Fred Pfost, Brian Sanford, Katherine L. Puckett
  • Patent number: 5365452
    Abstract: At least first and second adjacent parts supply tables of a parts supply apparatus are controlled so as to avoid unnecessary movement of a one of the parts supply tables not being used in successive parts supply operations, while at the same time, ensuring that the parts supply tables are sufficiently close to one another at the time of switching over between the parts supply tables to thereby reduce the duration of the switching operation. Alternately, the two parts supply tables are moved together from one position to another to maintain an interval therebetween which allows for a rapid switch-over between the parts supply tables when necessary. However, the rate at which the parts supply table in use is moved is greater than the rate at which the parts supply table not in use is moved, whereby the two parts supply tables come to a rest at different times to thereby reduce impact vibrations.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: November 15, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeki Imafuku, Noriaki Yoshida, Takeshi Takeda, Takashi Shimizu
  • Patent number: 5363290
    Abstract: An improved irrigation controller of solid state design utilizes a microcomputer which retains and executes a watering schedule input by a user through data input means. One of the parameters of system operation is the times of day in which irrigation will start when the current day is selected to be active. The controller of this invention uses a slide potentiometer having multiple sliders which may be moved in a single slideway for setting multiple start times determined by the slider positions. In addition, a hot post terminal is provided in the controller connected to ground. This terminal can be used to determine station assignment by touching the station wires to the terminal as power is applied along a common line to the actuating devices, i.e. solenoids, of the various stations.
    Type: Grant
    Filed: July 13, 1993
    Date of Patent: November 8, 1994
    Assignee: The Toro Company
    Inventors: Leonard W. Doup, Kurt Maloney
  • Patent number: 5361198
    Abstract: Through a localized compact workstation (104), the operator is offered all the monitoring, alarming and control functions which have been previously dispersed over many control panels located throughout the control room (100). The information display hierarchy is composed of an IPSO overview display (122), video display units (108) preferably based on CRT technology and qualified video display units (116) preferably based on solid state flat panel display technology. Associated with each display unit is an individual, independent control module to allow process and component control. One control module (112) supports non-safety control functions and avoids separate controllers for components and process control. Another control module (118) is a qualified system which supports safety system control functions and avoids separate controllers for component and process control.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: November 1, 1994
    Assignee: Combustion Engineering, Inc.
    Inventors: Daryl L. Harmon, David S. Jamison, Kenneth Scarola
  • Patent number: 5361221
    Abstract: A residue calculation circuit which can achieve increase of the calculation speed and reduction of the scale of an integrated circuit.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: November 1, 1994
    Assignee: Sony Corporation
    Inventor: Tadao Fujita
  • Patent number: 5359610
    Abstract: An encoding system encodes up to 64 kilobytes of data using a binary Bose-Chaudhuri-Hocquenghem (BCH) error detection code. The code has as a generator polynomial g(x):g(x)=(x.sup.20 +x.sup.17 +1)*(x+1)*(x.sup.20 +x.sup.3 +1)*(x.sup.20 +x.sup.3 +x.sup.2 +X+1)which in octal representation is:g(x)=4400001*3*4000011*4000017where * and + represent Galois Field multiplication and addition, respectively. The associated primitive polynomial is x.sup.20 +x.sup.17 +1. The encoder encodes the data using a code based on a polynomial f(x), which is g(x) multiplied by a factor, b(x)=x.sup.3 +x+1, or:f(x)=(x.sup.3 +x+1)*(x.sup.20 +x.sup.17 +1)*(x+1)*(x.sup.20 +x.sup.3 +1)*(x.sup.20 +x.sup.3 +x.sup.2 +X+1)which in octal representation is:f(x)=13*4400001*3*4000011*4000017The inclusion of the factor in the code enhances the code's burst detecting capabilities. The code is capable of detecting 7 random errors, and a single burst error of up to 64 bits or double burst errors of up to 24 bits each.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: October 25, 1994
    Assignee: Digital Equipment Corporation
    Inventor: Lih-Jyh Weng
  • Patent number: 5359520
    Abstract: An adaptive control includes a digital error correction system (DECS) to reduce control system error to near zero by anticipating a problem and feeding forward in time a correction to deal with the problem before it happens. The adaptive control is used in a controlled system of the kind which is cyclical in operation and which operates in response to repetitive cycle commands so that the operation of the system is substantially predictable for a significant number of cycles of operation. The adaptive control is incorporated in a spatial chopping or scanning telescope system of the kind in which a telescope mirror is moved in repetitive cycle motions and in a rigidly prescribed pattern between varied orientations and wherein the mirror is held for a prescribed, relatively long period of time in each orientation and is moved rapidly in a relatively short period of time from one orientation to another.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: October 25, 1994
    Assignee: Lockheed Missiles & Space Company, Inc.
    Inventors: Jean-Noel Aubrun, Kenneth R. Lorell, Paul J. Reshatoff
  • Patent number: 5359507
    Abstract: Disclosed herein is a sequence controller capable of executing programmable sequence operations written in its sequence table. The sequence table comprises a group of input condition collecting instructions, a group of branch condition collecting instructions, a table instruction and a group of input instructions, and has an accumulator for combining such instructions organically and selectively to deal with various sequence operation conditions. Thus it is possible to provide complicated control operations by use of the sequence table. The sequence table also contains a step number storing section which stores the original step number upon transition from one step to another, and a step return performing portion. When a predetermined branch condition is met, the step return performing portion initiates a return to the step stored in the section or to the step next thereto.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: October 25, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Noritaka Egami
  • Patent number: 5359524
    Abstract: The present invention includes processing circuitry (11) interfacing with a multi-process environment (10) for performing a method of determining an average batch size. A processor (12) receives input parameters corresponding to characteristics of the multi-process environment (10) from interfacing circuitry (18). These input parameters generate a first utilization factor which generates a first estimate of the average batch size during a first iteration step. A second utilization factor and in turn a second estimate of the average batch size are generated during a second iteration step.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: October 25, 1994
    Inventor: Darius Rohan
  • Patent number: 5357423
    Abstract: Apparatus and a method for controlling the power output of an ultrasonic generator to a transducer includes a variable impedance network circuit which is interposed between the generator and the transducer. Sensing circuits and a microprocessor are coupled to the input of the transducer so that the total impedance Z.sub.T, the transducer impedance in free air Z.sub.FA and the load impedance Z.sub.L may be calculated and the network impedance Z.sub.NW may be set for a bonding operation to maintain the power level P.sub.L or the impedance Z.sub.L at a desired predetermined level.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: October 18, 1994
    Assignee: Kulicke and Soffa Investments, Inc.
    Inventors: James M. Weaver, Michael J. Sowers
  • Patent number: 5357421
    Abstract: Parallel-working controllers are provided to control processes whose performance is dependent upon working points. These controllers are allocated to selected working points, and their output signals are put into effect, after being weighted, in dependence upon the working-point parameters that have a dominant influence on the process performance. The method is preferably implemented using fuzzy logic. A transition which is smooth in terms of interpolation is possible among the controllers.
    Type: Grant
    Filed: February 3, 1993
    Date of Patent: October 18, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wilfried Tautz, Georg Weihrich
  • Patent number: 5357425
    Abstract: A method and apparatus are disclosed for inherent, reliable control of real time systems. The technique is based on asynchronously scheduling a plurality of sensor sampling cycles over a suitable sampling interval. The corresponding plurality of sampling signals so obtained are temporally redundant and out of phase with respect to one another. This plurality of sampling signals is processed by a corresponding plurality of controllers. Thereafter, a multiplexor means is used to alternately and asynchronously receive from each controller a subinterval portion of each of the plurality of signals corresponding to each of the plurality of controllers. In this way the sampling interval is responsively partitioned into subintervals wherein each controller of the plurality effectively controls the system for each respective subinterval. Concurrent multiple control of each interval inherently masks and compensates for faults or failures.
    Type: Grant
    Filed: February 13, 1991
    Date of Patent: October 18, 1994
    Assignee: General Electric Company
    Inventor: Karl D. Minto
  • Patent number: 5357457
    Abstract: An adder circuit for adding two 16-bit data to each other includes 16 full adders and three carry look ahead circuits. A plurality of full adders excluding two ones provided on the least significant bit side and two ones provided on the most significant bit side are classified into three groups. Each of the groups includes four full adders. A single carry look ahead circuit is provided for the four full adders forming each group.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideyuki Terane