Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

Abstract: A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: An apparatus for executing fixed width instructions in a multiple execution unit system has a device for fetching instructions from a memory, and a decoder for decoding each fetched instruction in turn. A determination is made as to whether each decoded instruction includes a portion to fetch a locally stored instruction from a local store. If it does, the locally stored instruction is fetched and locally stored portion are executed.

Abstract: A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file.

Abstract: An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.

Abstract: A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.

Abstract: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates.

Abstract: Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.

Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Abstract: A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.

Abstract: A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

Abstract: A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract: A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode.

Abstract: A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

Abstract: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the hardware facility is absent from the data processing system, the candidate instruction is substituted with a second set of instructions.

Abstract: The method and system for data speculation of multicore systems are disclosed. In one embodiment, a method includes dynamically determining whether a current speculative load instruction and an associated store instruction have same memory addresses in an application thread in compiled code running on a main core using a dynamic helper thread running on a idle core substantially before encountering the current speculative load instruction. The instruction sequence associated with the current speculative load instruction is then edited by the dynamic helper thread based on the outcome of the determination so that the current speculative load instruction becomes a non-speculative load instruction.

Abstract: A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine initially saves the state of the processor and then executes an instruction to switch to protected mode. When in protected mode, the routine transfers control to 32-bit code. The 32-bit code uses a global descriptor table that is different from that used by the interrupted operating system. When the 32-bit code completes, it restores the saved processor state and returns from the interrupt by executing an RSM instruction.