Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10?4 mg/cm2 to 0.1 mg/cm2.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

Abstract: A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the semiconductor layer, and a plurality of the unit cells is coupled in a chain manner to form a unit chain structure with a constriction. The certain shape of the unit cell is defined by an outer edge of a virtual region of the semiconductor layer defined so as to include the source region and the well region inside and by respective outer edges of the source region and the well region at a joint with a different unit cell. An active region is composed of a plurality of the unit chain structures. The unit chain structures are arranged so as to avoid generation of a gap between the unit cells of adjacent ones of the unit chain structures.

Abstract: Embodiments of the invention provide an organic thin film transistor, an organic thin film transistor array substrate and a display device. The organic thin film transistor comprises a transparent substrate; source and drain electrodes formed on the transparent substrate; an active layer formed on the transparent substrate by an organic semiconductor material and disposed between the source and drain electrodes; a gate insulating layer formed on the active layer; a gate electrode formed on the gate insulating layer; and first and second banks disposed on the transparent substrate, inner sides of the first and second banks being covered by the source and drain electrodes, respectively.

Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n? layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.

Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section.

Abstract: An organic light emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a flexible substrate and a plurality of OLEDs. The flexibility substrate includes at least one curved portion. The OLEDs are positioned in every pixel area that is set on the flexible substrate and includes a pixel electrode, an organic emission layer, and a common electrode. At least one OLED that is positioned at a curved portion in the OLEDs is formed in a lens shape and concentrates light toward the center of a pixel area.

Abstract: A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n+ substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n+ substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall.

Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containing III group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion.

Abstract: A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.

Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.

Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.

Abstract: A semiconductor light emitting device which produces mixed light of a desired emission color by a combination of a semiconductor light emitting element and a wavelength converting layer containing a fluorescent substance, and a vehicle lamp including the semiconductor light emitting device. The wavelength converting layer has different wavelength conversion characteristics respectively at its portion covering an area of relatively high current density at light emission operation of the semiconductor light emitting element and at its portion covering an area of relatively low current density so as to reduce chromaticity difference over the light extraction surface of the mixed light due to non-uniformity of current density in the light emitting layer at light emission operation.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: A light emitting device having a high definition, a high aperture ratio and a high reliability is provided. The present invention realizes a high definition and a high aperture ratio for a flat panel display of full colors using luminescent colors of red, green and blue without being dependent upon the film formation method and deposition precision of an organic compound layer by forming the laminated sections 21, 22 by means of intentionally and partially overlapping different organic compound layers of adjacent light emitting elements. Moreover, the protective film 32a containing hydrogen is formed and the drawback in the organic compound layer is terminated with hydrogen, thereby realizing the enhancement of the brightness and the reliability.

Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.

Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.

Abstract: A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.

Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.