Patents Examined by Jessica Manno
  • Patent number: 10297682
    Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Hidenori Takahashi
  • Patent number: 10177534
    Abstract: A device is provided in which a light emitting semiconductor structure is excited by an electron beam that impacts a region of a lateral surface of the light emitting semiconductor structure at an angle to the normal of the lateral surface that is non-zero. The non-zero angle can be configured to cause excitation in a desired region of the light emitting semiconductor structure. The device can include wave guiding layer(s) and/or other features to improve the light generation and/or operation of the device.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Patent number: 10153613
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 11, 2018
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 10090294
    Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall insulating film, including a side wall insulating film, formed along side walls of the diode trench, and a bottom wall insulating film, formed along a bottom wall of the diode trench and having a thickness greater than a thickness of the side wall insulating film, and a bidirectional Zener diode, formed on the bottom wall insulating film inside the diode trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 2, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Nishida, Shinpei Ohnishi, Kentaro Nasu
  • Patent number: 10090642
    Abstract: A hybrid external cavity laser and a method for configuring the laser having a stabilized wavelength is disclosed. The laser comprises a semiconductor gain section and a volume Bragg grating, wherein a laser emission from the semiconductor gain section is based on a combination of a reflectivity of a front facet of the semiconductor gain section and a reflectivity of the volume Bragg grating and the reflectivity of the semiconductor gain section and the volume Bragg grating are insufficient by themselves to support the laser emission. The hybrid cavity laser further comprises an etalon that provides further wavelength stability.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 2, 2018
    Assignee: Innovative Photonic Solutions, Inc.
    Inventors: John C. Connolly, Donald E Ackley, Scott L. Rudder, Harald R. Guenther
  • Patent number: 10083943
    Abstract: A method of manufacturing a light-emitting device includes steps of: preparing at least one substrate having a plurality of through holes; providing an electric wire on a rear surface side of the substrate so that a plurality of portions of the electric wire communicates with a front surface side of the substrate at the plurality of through holes of the substrate; and respectively mounting a plurality of light-emitting diodes to the respective portions of the electric wire that communicate with the front surface side of the substrate.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 25, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Yukitoshi Marutani, Hiroto Tamaki, Tadaaki Miyata
  • Patent number: 10083924
    Abstract: A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: September 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Yuichi Kawano
  • Patent number: 10056322
    Abstract: An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a substrate having a through hole; an insulative resin layer formed on a surface of the substrate and including a conductive via; a wiring layer disposed on the substrate with the insulative resin layer interposed therebetween; an inorganic adhesive layer formed only on a side surface of the through hole; and a through electrode filled in a connection hole which is formed by the inorganic adhesive layer in the through hole so as to penetrate between both surfaces of the substrate, wherein the through electrode is electrically connected to the wiring layer via the conductive via, and a thermal expansion coefficient of the inorganic adhesive layer is larger than a thermal expansion coefficient of the substrate and smaller than a thermal expansion coefficient of the through electrode.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 21, 2018
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Koji Imayoshi, Syuji Kiuchi
  • Patent number: 10056488
    Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Sameer Pradhan, Jeanne Luce
  • Patent number: 10043892
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over the at least on fin. The dielectric film is irradiated with ultra violet (UV) radiation from a single UV source.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ying Li, Ming-Shiou Kuo, Wei-Ching Wu, Zong-Han Li, Ching-Lun Lai
  • Patent number: 10020639
    Abstract: A laser diode arrangement comprising: at least one semiconductor substrate; at least two laser stacks based on the AlInGaN material system, each laser stack having an active zone, wherein at least one of the at least two laser stacks comprises a two-dimensional structure of laser diodes; and at least one intermediate layer. The laser stacks and the intermediate layer are grown monolithically on the semiconductor substrate. The intermediate layer is arranged between the laser stacks. The active zone of the first laser stack can be actuated separately from the active zone of the at least one further laser stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 10, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Alfred Lell, Martin Strassburg
  • Patent number: 10002989
    Abstract: The present invention provides a method for producing a semiconductor light-emitting device in which fine protrusions and recesses are formed on a bottom surface between the protrusions on a surface of a substrate. The method comprises forming a first resist pattern on a nitrogen surface of the substrate, forming a plurality of first protrusions on the nitrogen surface of the substrate, and forming a plurality of second protrusions on the nitrogen surface of the transparent nitride-based substrate. In forming the first protrusions, the plurality of first protrusions and a bottom surface between the first protrusions are formed by dry etching. In forming the second protrusions, the plurality of second protrusions having a height lower than the height of the first protrusions are formed on the bottom surface by wet etching without removing the first resist pattern subjected to dry etching.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: June 19, 2018
    Assignee: TOYOTA GOSEI CO., LTD.
    Inventors: Kimiyasu Ide, Shingo Totani
  • Patent number: 9997889
    Abstract: A laser device includes a gain medium configured to receive an excitation light and emit a fluorescence signal based on an amount of stored excitation light accumulated in the gain medium. The laser device includes a pump source configured to pump the excitation light to the gain medium using a supply voltage. The laser device includes one or more photodetectors configured to detect the fluorescence signal. The laser device also includes a comparator configured to generate an alert signal indicating an intensity of the detected fluorescence signal is greater than a threshold. The alert signal can trigger certain actions to occur for disrupting a destructive lasing action including one or more of ceasing output of the supply voltage to the pump source, spoiling an optical cavity to obstruct lasing action through the gain medium, or inserting a seed light to extract gain from the gain medium in a non-destructive manner.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: June 12, 2018
    Assignee: LOCKHEED MARTIN COHERENT TECHNOLOGIES, INC.
    Inventor: Bruce G. Tiemann
  • Patent number: 9991673
    Abstract: An optical package having a patterned submount, an optoelectronic device mounted to the patterned submount, a spacer affixed on one side to the patterned submount, the spacer having a bore hole therethrough wherein the optoelectronic device is positioned, and an optical element affixed to the spacer on a side opposite the patterned submount and covering the spacer bore hole. The patterned submount may be a circuit board. The optoelectronic device may be a VCSEL. The spacer may be affixed to the circuit board, for example, using an epoxy preform or an adhesive laminate. The spacer may, for example, be manufactured from a sheet of stainless steel or from a circuit board. The optical element may be, for example, a diffuser, a concave lens, a convex lens, a holographic element, polarizers, or diffraction gratings. The optical element may be affixed to the spacer using an epoxy preform or an adhesive laminate.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 5, 2018
    Assignee: Vixar, Inc.
    Inventors: William Hogan, Mary Brenner
  • Patent number: 9985417
    Abstract: Gallium and nitrogen containing optical devices operable as laser diodes are disclosed. The devices include a gallium and nitrogen containing substrate member, which may be semipolar or non-polar. The devices include a chip formed from the gallium and nitrogen substrate member. The chip has a width and a length. The devices have a cavity oriented substantially parallel to the length of the chip, a dimension of less than 120 microns characterizing the width of the chip, and a pair of etched facets configured on the cavity of the chip. The pair of etched facets includes a first facet configured at a first end of the cavity and a second facet configured at a second end of the cavity.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 29, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Hua Huang
  • Patent number: 9972703
    Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, James A. Teplik
  • Patent number: 9966724
    Abstract: A laser includes first through fourth gain media, first through fifth wavelength selective filters, and first through fourth wavelength selective mirrors. The first through fourth gain media emit laser beams of different wavelengths. Each of the first through fifth wavelength selective filters includes first through fourth input/output ports. The fifth wavelength selective filter selects light of periodic wavelengths. The first through fourth wavelength selective filters have their respective first input/output ports connected to the first through fourth gain media, respectively, have their respective fourth input/output ports connected to the first through fourth wavelength selective mirrors, respectively, and have their respective second input/output ports connected to the first through fourth input/output ports, respectively, of the fifth wavelength selective filter.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 8, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Kazumasa Takabayashi, Tsuyoshi Yamamoto
  • Patent number: 9966735
    Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
  • Patent number: 9941662
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 9922944
    Abstract: A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is formed to cover the first film (3) and second film (4). After forming the surface protection film (5), a reverse surface of the semiconductor wafer (1) is etched with a chemical liquid. The first film (3) is formed on an outer peripheral section of the semiconductor wafer (1). The second film (4) is not formed on the outer peripheral section of the semiconductor wafer (1). The first film (3) and the surface protection film (5) are adhered to each other in the outer peripheral section of the semiconductor wafer (1). The first film (3) has a higher adhesion to the surface protection film (5) than the second film (4).
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: March 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shunichi Watabe