Patents Examined by Jey Tsai
  • Patent number: 9523898
    Abstract: Provided is a display apparatus, including a substrate including: a pixel electrode; an organic insulating film; a common electrode laminated on the organic insulating film so as to be opposed to the pixel electrode via an insulating layer; a common signal line connected to the common electrode; and a transistor configured to apply, to the pixel electrode, a voltage signal input to a signal line. The pixel electrode is connected to a source electrode of the transistor via a through hole formed through the organic insulating film. The through hole includes, in at least one extending portion formed by retreating the organic insulating film toward an outer side of the through hole, a stepped portion formed by laminating a part of the common signal line.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: December 20, 2016
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Norihisa Kakinuma, Teruhisa Nakagawa, Masahiro Ishii, Daisuke Kajita
  • Patent number: 9397233
    Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 19, 2016
    Assignee: North Star Innovations Inc.
    Inventors: Ronghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
  • Patent number: 8956948
    Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Bin Yang
  • Patent number: 8735187
    Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line on the substrate and crossing each other to define a pixel region, a thin film transistor connected to the gate line and the data line, a first passivation layer on the thin film transistor and having a first unevenness structure at its top surface, an auxiliary unevenness layer on the first passivation layer and having a first roughness structure at its top surface, and a reflector on the auxiliary unevenness layer, the reflector having a second unevenness structure due to the first unevenness structure of the first passivation layer and a second roughness structure due to the first roughness structure of the auxiliary unevenness layer, the second roughness structure having smaller patterns than the second unevenness structure.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: May 27, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Kyun Lee, Jae-Young Oh
  • Patent number: 8704291
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 22, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8685819
    Abstract: A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 1, 2014
    Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche Scientifique, Universite Joseph Fourier
    Inventors: Julien Buckley, Karim Aissou, Thierry Baron, Gabriel Molas
  • Patent number: 8686559
    Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
    Type: Grant
    Filed: September 8, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, Michael Ignatowski
  • Patent number: 8679936
    Abstract: An anneal recipe is provided to tighten the distribution of resistance values in the manufacture of semiconductor integrated circuits. An adjusted amount of dopant is implanted to compensate for a shift in the distribution of resistance values associated with the anneal recipe. The distribution tightening can be effectuated by including an ammonia gas flow in the anneal recipe.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: March 25, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Thanas Budri, Jerald M. Rock, Randy Supczak
  • Patent number: 8680595
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • Patent number: 8674434
    Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Venkatesan Ananthan
  • Patent number: 8669145
    Abstract: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Diane C. Boyd, Huilong Zhu
  • Patent number: 8664658
    Abstract: An n-channel transistor or a p-channel transistor provided with a second gate electrode for controlling a threshold voltage in addition to a normal gate electrode is used for a complementary logic circuit. In addition, an insulated gate field-effect transistor with an extremely low off-state current is used as a switching element to control the potential of the second gate electrode. A channel formation region of the transistor which functions as a switching element includes a semiconductor material whose band gap is wider than that of a silicon semiconductor and whose intrinsic carrier density is lower than that of silicon.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 8643066
    Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung L. Min, James D. Burnett, Leo Mathew
  • Patent number: 8633589
    Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: January 21, 2014
    Assignee: Invensas Corporation
    Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
  • Patent number: 8597960
    Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, Michael Ignatowski
  • Patent number: 8586430
    Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Komeda
  • Patent number: 8565016
    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Donald L. Yates, Joel A. Drewes
  • Patent number: 8559163
    Abstract: The present invention relates to a reaction vessel for producing a capacitor element, which is used for forming a semiconductor layer by means of energization on two or more electric conductors each having formed on the surface thereof a dielectric layer simultaneously, by immersing the electric conductors into an electrolyte in the reaction vessel, the vessel comprising two or more negative electrode plates corresponding to the individual electric conductors and two or more constant current sources electrically connected to each of the negative electrode plates; production method for a group of capacitor elements using the reaction vessel and a capacitor using the capacitor element. According to the present invention, a large number of capacitors which each uses a semiconductor layer as one part electrode with a narrow appearance capacitance distribution can be obtained simultaneously.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: October 15, 2013
    Assignee: Showa Denko K. K.
    Inventors: Kazumi Naito, Katutoshi Tamura
  • Patent number: 8557045
    Abstract: An apparatus and method for manufacturing thin-film CdS/CdTe photovoltaic modules in a vacuum environment. The apparatus deposits CdS and CdTe layers onto a substrate using heated pocket deposition, a form of physical vapor deposition (PVD) in which a material thermally sublimes from a thermal sublimation source block and is deposited onto a substrate. The thermal sublimation source block includes a pocket having a lower surface into which an array of holes is formed to house plugs of deposition material. Upon heating, deposition material sublimes from a surface of each plug of deposition material, and the surface of each plug regresses into its corresponding hole while maintaining a constant surface area. The sublimation surface area of deposition material across the pocket remains substantially constant during an extended deposition process, and the deposition material is substantially free of undesired thermal radiation from the substrate.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: October 15, 2013
    Assignee: Colorado State University Research Foundation
    Inventors: Kurt L. Barth, Robert A. Enzenroth, Walajabad S. Sampath
  • Patent number: 8543201
    Abstract: A method of joining a connection member to a capacitor foil using a staking tool having a tip of less than 0.030? (0.762 mm) in diameter. Another embodiment couples multiple connection members of a capacitor together by edge-connecting each connection member to its substantially flush neighboring connection members. In one aspect, a capacitor includes a multi-anode stack connected at a first weld by a weld joint less than 0.060? (1.524 mm) in diameter and a tab attached to one of the anodes of the multi-anode stack at a second weld. In one aspect, an exemplary method joining one or more foils using a staking tool having a tip of less than approximately 0.060? (1.524 mm) in diameter. In another aspect, a capacitor including a capacitor case having an electrolyte therein and a high formation voltage anode foil having a porous structure and located within the capacitor case.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: September 24, 2013
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Michael J. O'Phelan, James M. Poplett, Robert R. Tong, Rajesh Iyer, Alexander Gordon Barr