Abstract: A fault tolerant 64-bit data-width peripheral component interconnect (PCI) bus system in a computer system that may recover from a fault(s) occurring on either the upper or lower 32-bit portions of a 64-bit data-width PCI bus. When a parity error is detected on one of either the upper or lower 32-bit portions of the 64-bit data-width PCI bus, the 32-bit portion not having the parity error is used to transfer data and the one having the parity error is inhibited from further use. The PCI bus may be dynamically configured for transfer of data at 64-bits per clock, or at 32-bits per clock over either the upper or lower portions of the PCI bus. New signals SWAP# and SWAP.sub.-- ACK# are used to accomplish the fault tolerant operation. 64-bit disable and swap enable bits in a PCI device command register are used to disable 64-bit data transfer, and swap data transfer from the lower portion to the upper portion of the PCI bus, respectively.