Patents Examined by Jim Dudek
  • Patent number: 5381107
    Abstract: In a time-base inversion type linear phase filter, an input signal is time-base inverted, and thereafter delayed. The delayed signal is time-base inverted back to the original time sequence and then filtered by a first IIR filter. First and second selectors alternately select the time-base inverted signal and the delayed signal in opposite phases to each other. Output signals of the selectors are filtered by second and third IIR filters and then alternately selected by a third selector. An output of the third selector is time-base inverted back to the original time sequence and added to an output of the first IIR filter. A nonlinear emphasis/de-emphasis apparatus is constituted by using this linear phase filter.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: January 10, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuo Hamamoto
  • Patent number: 5369308
    Abstract: A power transistor switching circuit includes a switching transistor. A switching signal triggers a control device which, via a delay device and a control amplifier applies a first control signal to a control electrode of the switching transistor. A thyristor is coupled to the control electrode of the switching transistor. The thyristor has a first trigger gate and a second trigger gate. A measuring circuit generates a measuring signal proportional to the current in the switching transistor. A comparison device compares the measuring signal with a reference signal for applying a second trigger signal to the thyristor second trigger gate. The control device includes a further control amplifier having an input coupled to the switching signal and an output which applies a further control signal to the first trigger gate. The delay device delays the first control signal with respect to the further control signal.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: November 29, 1994
    Assignee: U.S. Philips Corporation
    Inventors: Franciscus A. C. M. Schoofs, Johan C. Halberstadt
  • Patent number: 5369339
    Abstract: A circuit arrangement for operating a low-pressure mercury discharge lamp by a high-frequency current which includes a DC component and a high-frequency AC component. The circuit arrangement has a switching device for generating the high-frequency AC component from a supply voltage, an asymmetry device for rendering a first amplitude of the high-frequency AC component in a first polarization direction and a second amplitude of the high-frequency AC component in a second polarization direction unequal to one another, and a DC device for generating the DC component. The polarity of the DC component coincides with the polarization direction of the greater of the two amplitudes. Thus, striations in a low-pressure mercury discharge lamp operated on the circuit arrangement can be rendered invisible over a wide range of powers consumed by the lamp.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: November 29, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Jozef H. Reijnaerts
  • Patent number: 5369338
    Abstract: A plasma display panel (PDP) is disclosed which includes a plurality of anodes formed on an upper plate, a plurality of first sustaining electrodes and a plurality of alternating second sustaining electrodes and cathodes formed on a lower plate, and a dielectric coated on the first and second sustaining electrodes and cathodes. A method for driving the PDP includes the steps of initiating a discharge by supplying a potential higher than the discharge firing voltage to the anodes and cathodes, generating a predetermined potential between the cathodes and first sustaining electrodes to increase the voltage generated from the discharge-initiating step, supplying a voltage higher than a discharge sustaining voltage between the first and second sustaining electrodes to maintain the discharge, and supplying a narrow pulse to the cathodes for erasing the discharge.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: November 29, 1994
    Assignee: Samsung Electron Devices Co., Ltd.
    Inventor: Dae-il Kim
  • Patent number: 5367203
    Abstract: A system provides a uniform delay in crossovers in opposite directions of a variable input voltage relative to a reference voltage. A comparator is included for producing first and second comparison voltages in accordance with the relative magnitudes of the input and reference voltages. A clamping circuit provides first and second clamping voltages. A control circuit produces first and second control voltages dependent upon the individual occurrences of the first and second comparison voltages. The first control voltage is greater by a particular magnitude than the first clamping voltage. The second control voltage is less than the second clamping voltage by the particular magnitude.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: November 22, 1994
    Assignee: Brooktree Corporation
    Inventor: Wylie J. Plummer
  • Patent number: 5365193
    Abstract: A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: November 15, 1994
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Maurizio Zuffada, Gianfranco Vai, Marco Gregori, David Moloney, Giorgio Betti
  • Patent number: 5359294
    Abstract: A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).
    Type: Grant
    Filed: October 5, 1993
    Date of Patent: October 25, 1994
    Assignee: Motorola, Inc.
    Inventors: Jeffrey D. Ganger, Kelvin E. McCollough, Jules D. Campbell, Jr
  • Patent number: 5359295
    Abstract: A power amplifier is provided, wherein the output of a first transistor supplied with an input signal at the base thereof is supplied to the base of a second transistor, a current proportional to a collector current of the second transistor is supplied to the emitter of the first transistor by a current mirror circuit, a third transistor is provided for outputting an emitter current in accordance with a base-to-emitter voltage of the second transistor, and emitter currents of the second and third transistors, in accordance with an emitter potential level of the first transistor, is used as an output current. This configuration allows non-linear portions in the transistor characteristics to be cancelled by each other, thereby providing a power amplifier which presents a good linearity.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: October 25, 1994
    Assignee: Pioneer Electronic Corporation
    Inventor: Yasushi Nishimura
  • Patent number: 5357208
    Abstract: An integrated circuit is disclosed that includes a biquadratic filter in which the poles and zeroes are independently adjustable. The transfer function of the filter has a pair of zeroes in the numerator and a pair of complex conjugate poles in the denominator. The integrated circuit includes a first circuit for constructing the complex conjugate poles of the filter transfer function. The first circuit has an input port for receiving an input signal and an output port at which an output current representative of a filtered output signal is presented. The integrated circuit includes a second circuit for constructing, independently of the poles, the zeroes of the filter transfer function. The second circuit has an input port coupled to the input port of the first circuit for receiving the input signal. The second circuit includes a differentiator for differentiating the input signal to produce a differentiated input signal.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: October 18, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Dale H. Nelson
  • Patent number: 5357213
    Abstract: A high-frequency wideband power amplifier, of the type comprising an amplifier stage with at least two transistors mounted as a differential stage, coupled at input and at output to a matching circuit further comprises, in order to convey each bias voltage to the amplifier stage, at least one high-frequency transmission line section with a length close to a quarter of the wavelength of the carrier of the signal to be amplified, the impedance of which, brought in parallel on each transistor, is negligible with respect to the high frequencies and the series impedance of which is negligible in the baseband of the signal to be amplified; the line sections conveying the bias voltages to the input of each transistor are identical to one another in length and in impedance, and the same is the case for the line sections conveying the bias voltages to the output of each transistor.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: October 18, 1994
    Assignee: Thomson-Lgt Laboratoire General des Telecommunications
    Inventors: Jean Michel, Jean-Claude Combe, Herminio de Faria
  • Patent number: 5357169
    Abstract: A switching apparatus for an interior light in a motor vehicle allows a user to set a delay period from the time when an off command was issued to a room light in the motor vehicle to the time when the light is actually turned off. The switching apparatus turns on and off a room light R in the motor vehicle. The switching apparatus comprises a limit switch 1 for issuing the off command to the room light R when a door is opened, a delay circuit 3 for generating a delay period from the time when the off command as issued to the light R to the time when the light R is to be turned off, and a regulator 4 for regulating the delay period generated by the delay circuit 3. It is possible for the user to set a desired lighting period by regulating the delay period, giving the motor vehicle high quality and versatility.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: October 18, 1994
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Morihiko Toyozumi, Nobuya Inamori
  • Patent number: 5357089
    Abstract: A circuit and method for protecting a transistor during operation transistor's BV.sub.CEO by limiting the reverse base current. The reverse base current is used to adjust the applied base-emitter voltage. Limiting the reverse base current keeps the collector and emitter currents within safe limits and thus extends the safe operating area of the transistor. The invention finds application as an overvoltage sensor and transistor protector circuit and is particularly applicable to implementation in an integrated circuit. The circuit may be combined with circuits for the protection of a transistor against excessive current and temperature in a high voltage linear regulator.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: October 18, 1994
    Assignee: Harris Corporation
    Inventor: John S. Prentice
  • Patent number: 5351013
    Abstract: A step attenuator using a PIN diode for use with microwave circuits. The step attenuator circuit provides for stepwise controlling the current applied to the microwave monolithic integrated circuit. The step attenuator circuit comprises a driver circuit and a attenuator circuit coupled thereto. The driver circuit that comprises a temperature sensor, a comparator circuit coupled to the temperature sensor for comparing the temperature value sensed by the temperature sensor to predetermined reference voltages and for providing a plurality of output signals that are indicative of a respective plurality of temperature values sensed by the temperature sensor, and a resistor network coupled to the comparator circuit that is adapted to set the respective values or current provided by the driver circuit.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: September 27, 1994
    Assignee: Hughes Aircraft Company
    Inventors: Raul I. Alidio, Clinton O. Holter
  • Patent number: 5349306
    Abstract: A distributed amplifier produced from monolithic microwave integrated circuit (MMIC) processes employs a bandpass filter structure as opposed to a low-pass filter network to enhance gain, efficiency and output power over wideband operation of 6 GHz to 18 GHz. Derivation of the preferred embodiment is shown from a three port circuit employing bandpass filter image-parameter half-sections.
    Type: Grant
    Filed: October 25, 1993
    Date of Patent: September 20, 1994
    Assignee: Teledyne Monolithic Microwave
    Inventor: Thomas R. Apel
  • Patent number: 5349305
    Abstract: A sampled-data, current-mode circuit implements analog functions in a standard digital process. Among sampled-data current-mode circuits, the current S/H (CSH) circuit is a key component. This fully differential CSH circuit was implemented in a 1.2 .mu.m N-well double-poly double metal CMOS technology adapted to 8-bit resolution at a 15 MHz sampling rate.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: September 20, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Chun-Fang Hsiao, Chung-Yu Wu, Chin-Cheng Chen
  • Patent number: 5347231
    Abstract: The invention is a novel charge sensitive preamplifier (CSP) which has no resistor in parallel with the feedback capacitor. No resetting circuit is required to discharge the feedback capacitor. The DC stabilization of the preamplifier is obtained by means of a second feedback loop between the preamplifier output and the common base transistor of the input cascode. The input transistor of the preamplifier is a Junction Field Transistor (JFET) with the gate-source junction forward biased. The detector leakage current flows into this junction. This invention is concerned with a new circuit configuration for a charge sensitive preamplifier and a novel use of the input Field Effect Transistor of the CSP itself. In particular this invention, in addition to eliminating the feedback resistor, eliminates the need for external devices between the detector and the preamplifier, and it eliminates the need for external circuitry to sense the output voltage and reset the CSP.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: September 13, 1994
    Assignee: Associated Universities, Inc.
    Inventors: Giuseppe Bertuccio, Pavel Rehak, Deming Xi
  • Patent number: 5345120
    Abstract: A swing limiting circuit for limiting the voltage across the input of a BiCMOS sense amplifier includes first and second bipolar transistors each having their collectors coupled to a first supply potential and their emitters coupled to the respective bases of a pair of bipolar transistors forming the sense amplifier. First and second pass gate devices are utilized to couple the respected bases of the first and second transistors to the bit lines running through the memory so as to limit the voltage drop appearing across the bases of the first and second transistors. A pair of NMOS devices are configured as source followers in parallel with the bipolar transistors to keep the voltage at the bases of the differential pair from dropping below a predetermined level.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: September 6, 1994
    Assignee: Intel Corporation
    Inventor: Gregory F. Taylor
  • Patent number: 5343164
    Abstract: A low power operational amplifier adjusts its output slew rate by providing additional bias current to its differential amplifier stage when the amplitude of the differential input signal exceeds a given threshold. The additional bias current provides an enhanced current for charging or discharging an internal compensating feedback capacitor of the operational amplifier. The power dissipation of the operational amplifier is kept low by employing FET transistors for the basic operational amplifier functions and by minimally biasing the slew rate enhancement circuitry associated with monitoring the amplitude of the differential input signal as well as providing the additional current to the differential amplifier stage when the amplitude of the differential input signal exceeds the given threshold.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: August 30, 1994
    Assignee: John Fluke Mfg. Co., Inc.
    Inventor: Todd E. Holmdahl
  • Patent number: 5343083
    Abstract: An analog/digital hybrid masterslice IC includes an analog circuit section formed by a CMOS analog section and an analog master section in which a plurality of basic blocks are arranged in array form, and a digital circuit section formed by a gate array section. The digital circuit section operates under a power source voltage lower than that supplied to the analog circuit section. The IC further includes a selector circuit disposed between the digital circuit section and the analog circuit section, for testing the analog circuit section and the digital circuit section independently from each other, and a level shift circuit disposed between the selector circuit and the analog master section, for amplifying an output level from the gate array section. The level shift circuit is fixedly built-in in a masterwafer substrate as a hard-macro. The arrangement ensures that there is no possibility of any digital noise entering the analog circuit.
    Type: Grant
    Filed: February 3, 1993
    Date of Patent: August 30, 1994
    Assignee: NEC Corporation
    Inventor: Mamoru Fuse