Abstract: A method of forming a bond pad area for an integrated circuit provides FSG in the dielectric layer while at the same time minimizes bond pad lift off. The method includes forming a first dielectric layer of fluorinated silicon glass (FSG) on a substrate, then forming an FSG barrier layer on the first dielectric layer. A second, non-FSG dielectric layer is formed on the FSG barrier layer. A barrier metal layer is then formed on the second dielectric layer. Finally, a metal layer is formed on the barrier metal layer. This metal layer provides the surface for adhesion to the bonding wire. The FSG barrier layer absorbs the atoms of fluorine diffused from the first dielectric layer. In this manner, fluorine is prevented from penetrating the second dielectric layer, thereby minimizing bond pad lift off between the second dielectric layer and the barrier metal layer. In one embodiment, the FSG barrier layer includes titanium and/or aluminum.