Abstract: A static memory processor for pattern recognition and an input data dimensionality reduction is provided having a multi-layer harmonic neural network and a classifier network. The multi-layer harmonic neural network receives a fused feature vector of the pattern to be recognized from a neural sensor and generates output vectors which aid in discrimination between similar patterns. The fused feature vector and each output vector are separately provided to corresponding positional king of the mountain (PKOM) circuits within the classifier network. Each PKOM circuit generates a positional output vector with only the element corresponding to the element of the fused feature vector or output vector having the highest contribution in its respective vector having a value corresponding to one. The positional output vectors are active in a multidimensional memory space and are read by a recognition vector array which generates class likelihood outputs determined by the occupied memory space.