Abstract: A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.
Type:
Grant
Filed:
December 20, 1984
Date of Patent:
May 19, 1987
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Mark S. Young, John Drew, Michael C. Shebanow