Patents Examined by John D. Sotomayor
  • Patent number: 6809682
    Abstract: A method for discriminating and tracking a target in a clutter cloud includes transmitting a radar signal at a signal bandwidth to: identify a range extent of a clutter cloud; determine a centroid and a velocity growth rate of the clutter cloud; and identify a direction of movement of the centroid of the clutter cloud. The method may also include locking a another radar signal having a greater signal bandwidth onto the centroid of the clutter cloud whereby the centroid is tracked within one radar range resolution bin; providing a delay line that includes at least two Doppler filters and is configured to cover a Doppler frequency range corresponding to a velocity growth rate of the clutter cloud; and processing a reflected radar signal corresponding to the greater signal bandwidth. The processing of the reflected radar signal may comprise passing the reflected radar signal through the delay line to mitigate a portion of the reflected signal that is reflected by the clutter cloud.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: October 26, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: J. Michael Madewell
  • Patent number: 5192956
    Abstract: The present invention is a system that performs code compression in stages where each stage includes two processing paths 36 and 38. The two paths allow bidirectional crossover cascade complementary code compression reducing the number processing stages to log.sub.2 N and reducing the number of processing by a factor of N/(2 log.sub.2 N) where N is the length of the code. Each path includes a delay provided by a delay unit 44 and each path arithmetically combines the data from its own path with data from the other path. The upper path 36 uses an adder 40 while the lower path uses an adder/substracter unit 42 which adds or subtracts depending on the phase of the transmitted complementary phase code. The delay provided in each stage increases in a binary progression with the delay of the last stage being N/2. A systolic processor 68 is the preferred embodiment although the invention could be implemented in a programmable digital signal processor.
    Type: Grant
    Filed: November 13, 1991
    Date of Patent: March 9, 1993
    Assignee: Westinghouse Electric Corp.
    Inventor: Henry E. Lee