Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Abstract: An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.

Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.

Abstract: An integrated semiconductor cascode circuit is provided that comprises an emitter layer, a first base area, a second base area, an intermediate area and a collector area. The first base area is arranged between the emitter layer and the intermediate area, and the second base area is arranged between the intermediate area and the collector area. A dielectric layer that is provided with a central opening is arranged between the first base area and the second base area. The invention also relates to a method for the production of said semiconductor cascode circuit.

Abstract: A method that locates a plurality of die for forming a plurality of packaged integrated circuits. A frame is placed over the support structure, wherein the frame includes a plurality of openings therein and each opening of the plurality of openings has at least two walls. Each die of a plurality of die is placed over the support structure, wherein each die has at least two adjacent edges. The relative placing of the frame and the die results in each die being in an opening of the plurality of openings. Encapsulant is applied to the plurality of die. Either or both of the plurality of die and frame are moved in relation to the other in a manner that causes the two adjacent edges of each die of the plurality of die to substantially abut to and align with the two walls of an opening of the plurality of openings.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.