Abstract: The dot data to be displayed is divided and stored in an even address graphic memory and an odd address graphic memory. When data to be revised (refreshed) bridges over adjacent word units having different addresses, the CPU generates the word address of the odd address graphic memory and new dot data to be displayed. A peripheral control circuit generates the word address signal and an address signal of the adjacent address of the even address graphic memory so as to revise the dot data which bridges over two word addresses. In this way, the dot data which bridges over two addresses can be revised by only one access operation to the memory.