Patents Examined by John F. Neibling
  • Patent number: 6812045
    Abstract: Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The measurement device may include an illumination system and a detection system. The illumination system and the detection system may be configured such that the system may be configured to determine multiple properties of the specimen. For example, the system may be configured to determine multiple properties of a specimen including, but not limited to, a characteristic of a specimen prior to, during, or subsequent to ion implantation. In this manner, a measurement device may perform multiple optical and/or non-optical metrology and/or inspection techniques.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 2, 2004
    Assignee: KLA-Tencor, Inc.
    Inventors: Mehrdad Nikoonahad, Ady Levy, Kyle A. Brown, Gary Bultman, Dan Wack, John Fielden
  • Patent number: 6780781
    Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: August 24, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Takahiro Odaka, Toshihiko Tanaka, Takashi Hattori, Hiroshi Fukuda
  • Patent number: 6684520
    Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: February 3, 2004
    Assignee: Xilinx, Inc.
    Inventors: Kevin T. Look, Shih-Cheng Hsueh
  • Patent number: 6348382
    Abstract: A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: February 19, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hung-Der Su, Chrong Jung Lin, Jong Chen, Wen-Ting Chu
  • Patent number: 6114221
    Abstract: A method for fabricating an interconnected multiple circuit chip structure by etching a first substrate to form protrusions on its surface. Then the protrusions are preferentially etched to produce a selected shape such as a tetragonal protrusion and an integrated circuit is then fabricated on the substrate. A second substrate is preferentially etched to form recesses having a selected shape that is the complement of the selected shape of the protrusions of the first substrate and then an integrated circuit is fabricated on the second substrate. The protrusions and recesses are coated with an electrically conductive metal such as aluminum. The first and second substrates are joined and aligned together such that the protrusions mate with the recesses and the structure is annealed such that the metal coatings thereon come into contact to electrically connect the integrated circuits on the substrates. The method can also be used to electrically connect multiple chips mounted back to front.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: William R. Tonti, Richard Q. Williams
  • Patent number: 4946502
    Abstract: A coating composition is disclosed for protecting from corrosion and oxidation in the hot condition carrier bars of pre-baked anodes and the emergent carbonaceous part of the anodes for the protection of aluminum in the Hall-Heroult process. The composition consists essentially of dry matter formed by calcium alumnate cement having an alumina content of at least 70% and a low content of impurities, magnesium spinel, and optionally, further alumina, together with water in the amount of 10 to 80% by weight of the total dry matter.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: August 7, 1990
    Assignee: Societe des Electrodes & Refractaires Savoie
    Inventors: Gabriel Audras, Bernard Samanos
  • Patent number: 4588489
    Abstract: A laminate of layers of dissimilar fibrous substances having an electrophoretic charge is produced by the electrodepositing technique in an apparatus comprising an inner electrode disposed horizontally and adapted to accumulate the aforementioned fibrous substances on the surface thereof and a plurality of electrodes of the opposite sign and as many electrodepositing zones for accommodating aqueous suspensions of the aforementioned fibrous substances both disposed horizontally and coaxially in a spaced relationship. The production of the laminate is effected by a method which comprises the steps of feeding at least to adjacent electrodepositing zones the aforementioned aqueous suspensions of fibrous substances causing the fibrous substances to be oriented in different directions at least in the aforementioned adjacent electrodepositing zones, and applying an electric potential between the opposite electrodes thereby allowing the fibrous substances to be accumulated on the surface of the inner electrode.
    Type: Grant
    Filed: June 7, 1983
    Date of Patent: May 13, 1986
    Assignee: Kureha Kagaku Kogyo Kabushiki Kaisha
    Inventors: Tohshichi Kitago, Masaharu Fujita, Seishiyo Kumagai
  • Patent number: 4544472
    Abstract: Coating for carbon electrodes used as anodes in the electrolysis of aluminum are disclosed. The coatings are aqueous and contain zinc chloride and powdered alumina.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: October 1, 1985
    Assignee: Nalco Chemical Company
    Inventor: Frederick V. Reven
  • Patent number: 3989532
    Abstract: An optical article, for example, a lens, window or mirror, at least part of the surface of which, and preferably the whole of which, is an inorganic oxide glass having a P.sub.2 O.sub.5 content of at least 52 mole %, and preferably 55 to 68.5 mole %, an alkaline earth content of 2.7 to 20 mole %, and a transformation temperature of not greater than 300.degree. C, the glass optionally containing B.sub.2 O.sub.3 and at least one alkali metal oxide.
    Type: Grant
    Filed: February 4, 1974
    Date of Patent: November 2, 1976
    Assignee: Imperial Chemical Industries Limited
    Inventors: Neil Hunter Ray, William Derek Robinson, Cyril John Lewis